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IDT7134SA55J Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT7134SA55J Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 9 page 6.04 9 IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION TRUTH TABLE I – READ/WRITE CONTROL(2) Left or Right Port (1) R/ W W W W W CE CE CE CE CE OE OE OE OE OE D0-7 Function X H X Z Port Disabled and in Power Down Mode, ISB2 or ISB4 XH X Z CER = CEL = H, Power Down Mode, ISB1 or ISB3 L L X DATAIN Data on port written into memory H L L DATAOUT Data in memory output on port X X H Z High impedance outputs 2720 tbl 11 NOTES: 1. AOL - A11L ≠ AOR - A11R 2. "H" = HIGH, "L" = LOW, "X" = Don’t Care, and "Z" = High-impedance FUNCTIONAL DESCRIPTION The IDT7134 provides two ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected ( CE high). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control ( OE). In the read mode, the port’s OE turns on the output drivers when set LOW. Non-contention READ/ WRITE conditions are illustrated in the table below. 2720 drw 13 IDT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range Blank B P C J L48 F 20 25 35 45 55 70 LA SA 7134 Commercial (0 °C to +70°C) Military (–55 °C to +125°C) Compliant to MIL-STD-883, Class B 48-pin Plastic DIP (P48-1) 48-pin Ceramic DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) Speed in nanoseconds Low Power Standard Power 32K (4K x 8-Bit) Dual-Port RAM Commercial Only |
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