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IDT71V421L55J Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT71V421L55J Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 14 page 6.42 IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 7 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. 'X' in part numbers indicates power rating (S or L). 5. For Master/Slave combination, tWC = tBAA + tWP, since R/ W = VIL must occur after tBAA. Symbol Parameter 71V321X25 71V421X25 Com'l & Ind 71V321X35 71V421X35 Com'l Only 71V321X55 71V421X55 Com'l Only Unit Min. Max. Min. Max. Min. Max. WRITE CYCLE tWC Write Cycle Time (5) 25 ____ 35 ____ 55 ____ ns tEW Chip Enable to End-of-Write 20 ____ 30 ____ 40 ____ ns tAW Address Valid to End-of-Write 20 ____ 30 ____ 40 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 20 ____ 30 ____ 40 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 12 ____ 20 ____ 20 ____ ns tHZ Output High-Z Time (1,2) ____ 12 ____ 15 ____ 30 ns tDH Data Hold Time (3) 0 ____ 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1,2) ____ 15 ____ 15 ____ 30 ns tOW Output Active from End-of-Write(1,2) 0 ____ 0 ____ 0 ____ ns 3026 tbl 10 |
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