IDT72255L10G datasheet(2/30 Pages) IDT

Part #	IDT72255L10G

Description	CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72255/72265 SyncFIFO

™

8,192 x 18, 16,384 x 18

automatically on the outputs, no read operation required. The

state of the FWFT/SI pin during Master Reset determines the

mode in use.

The IDT72255/72265 FIFOs have five flag functions,

EF/

OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input

Ready), and

HF (Half-full Flag). The EF and FF functions are

selected in the IDT Standard Mode.

The

IR and OR functions are selected in the First Word Fall

Through Mode.

IR indicates that the FIFO has free space to

receive data.

OR indicates that data contained in the FIFO is

available for reading.

HF is a flag whose threshold is fixed at the half-way point in

memory. This flag can always be used irrespective of mode.

PAE, PAF can be programmed independantly to any point

in memory. They, also, can be used irrespective of mode.

Programmable offsets determine the flag threshold and can

be loaded by two methods: parallel or serial. Two default

offset settings are also provided, such that

PAE can be set at

127 or 1023 locations from the empty boundary and the

PAF

threshold can be set at 127 or 1023 locations from the full

boundary. All these choices are made with

LD during Master

Reset

.

In the serial method,

SEN together with LD are used to load

the offset registers via the Serial Input (SI). In the parallel

method,

WEN together with LD can be used to load the offset

registers via Dn.

REN together with LD can be used to read the

offsets in parallel from Qn regardless of whether serial or

parallel offset loading is selected.

During Master Reset (

MRS), the read and write pointers are

set to the first location of the FIFO. The FWFT line selects IDT

Standard Mode or FWFT Mode. The

LD pin selects one of two

partial flag default settings (127 or 1023) and, also, serial or

parallel programming. The flags are updated accordingly.

The Partial Reset (

PRS) also sets the read and write

pointers to the first location of the memory. However, the

mode setting, programming method, and partial flag offsets

are not altered. The flags are updated accordingly.

PRS is

useful for resetting a device in mid-operation, when repro-

TQFP (PN64-1, order code: PF)

STQFP (PP64-1, order code: TF)

TOP VIEW

PIN 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

FS

VCC

GND

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q17

Q16

GND

Q15

Q14

VCC

Q13

Q12

Q11

GND

Q10

Q9

Q8

Q7

Q6

GND

3037 drw 02

PIN CONFIGURATIONS

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