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IDT7134SA20L48 Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7134SA20L48 Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 9 page 6.04 7 IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6) (CONT'D) 7134X45 7134X55 7134X70 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 45 — 55 — 70 — ns tEW Chip Enable to End-of-Write 40 — 50 — 60 — ns tAW Address Valid to End-of-Write 40 — 50 — 60 — ns tAS Address Set-up Time 0 — 0 — 0 — ns tWP Write Pulse Width 40 — 50 — 60 — ns tWR Write RecoveryTime 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 20 — 25 — 30 — ns tHZ Output High-Z Time (1, 2) —20 — 25 — 30 ns tDH Data Hold Time (3) 3— 3 — 3— ns tWZ Write Enabled to Output in High-Z (1, 2) —20 — 25 — 30 ns tOW Output Active from End-of-Write (1, 2, 3) 3— 3 — 3— ns tWDD Write Pulse to Data Delay (4) —70 — 80 — 90 ns tDDD Write Data Valid to Read Data Delay (4) —45 — 55 — 70 ns NOTES: 1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. (Commercial only), 0 °C to +70°C temperature range . 6. “X” in part number indicates power rating (SA or LA). TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1) 2720 tbl 10 2. CEL = CER = VIL. OE"B" = VIL. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". NOTES: 1. Write cycle parameters should be adhered to, in order to ensure proper writing. 2720 drw 10 R/ W "A" VALID tWC MATCH VALID MATCH tWP tDW tWDD tDDD ADDR "A" DATAIN "A" DATAOUT "B" ADDR "B" tAW |
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