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IDT723612L15PF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT723612L15PF Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 29 page  10 COMMERCIAL TEMPERATURE RANGE IDT723612 BiCMOS SyncBiFIFO ™ 64 x 36 x 2 Synchronized Synchronized Number of Words to CLKB to CLKA in the FIFO1(1) EFB EFB AEB AEB AFA AFA FFA FFA 0L L H H 1 to X H L H H (X+1) to [64-(X+1)] H H H H (64-X) to 63 H H L H 64 H H L L Synchronized Synchronized Number of Words to CLKB to CLKA in the FIFO(1) EFA EFA AEA AEA AFB AFB FFB FFB 0L L H H 1 to X H L H H (X+1) to [64-(X+1)] H H H H (64-X) to 63 H H L H 64 H H L L transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and EFB is HIGH (see Table 3). The setup and hold time constraints to the port clocks for the port chip selects ( CSA, CSB) and write/read selects (W/ RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port chip select and write/read select may change states during the setup and hold time window of the cycle. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one an- other. EFA, AEA, FFA, and AFA are synchronized by CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. EMPTY FLAGS ( EFA EFA, EFB EFB) The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag is HIGH, new data can be read to the FIFO output register. When the empty flag is LOW, the FIFO is empty and attempted FIFO reads are ignored. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an empty flag monitors a write-pointer and read- pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the empty flag synchronizing clock. Therefore, an empty flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set HIGH by the second LOW-to-HIGH transition of the synchro- nizing clock, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on an empty flag synchroniz- ing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first syn- chronization cycle. FULL FLAG ( FFA FFA, FFB FFB) The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full flag monitors a write-pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the full flag synchronizing clock. Therefore, a full flag is LOW if less than two cycles of the full flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the full flag synchronization clock after the read sets the full flag HIGH and the data can be written in the following clock cycle. A LOW-to-HIGH transition on a full flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first syn- chronization cycle. ALMOST EMPTY FLAGS ( AEA AEA, AEB AEB) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An almost-empty flag is LOW when the FIFO contains Table 4. FIFO1 Flag Operation Table 5. FIFO2 Flag Operation Note: 1. X is the value in the almost-empty flag and almost-full flag offset register. |
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