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IDT71V421L55PF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT71V421L55PF Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 14 page 6.42 IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 2 IDT71V321/421J J52-1(4) 52-Pin PLCC Top View(5) INDEX I/O A A A A A A A A A I/O I/O I/O 1L 2L 3L 4L 5L 6L 7L 8L 9L 0L 1L 3L 2L OER A A A A A A A A A A NC I/O 0R 1R 2R 3R 4R 5R 6R 7R 8R 9R 7R 1 2 3 4 5 6 747 48 49 50 51 52 9 8 10 11 12 13 14 15 16 17 18 19 20 27 26 25 24 23 22 21 33 32 31 30 29 28 35 34 36 37 38 39 40 41 42 43 44 45 46 3026 drw 02 , Pin Configurations(1,2,3) Description The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communica- tions. The IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap- plications results in full speed, error-free operation without the need for additional discrete logic. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (L) versions offer battery backup data retention capability, with each Dual- Port typically consuming 200µW from a 2V battery. The IDT71V321/IDT71V421 devices are packaged in a 52-pin PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP (super thin quad flatpack). INDEX IDT71V321/421PF or TF PP64-1(4) & PN64-1(4) 64-Pin STQFP 64-Pin TQFP Top View(5) 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 40 39 38 37 36 35 34 47 48 33 I/O6R N/C A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O7R OER N/C N/C I/O2L A0L OEL A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L N/C N/C 3026 drw 03 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PP64-1 package body is approximately 10mm x 10mm x 1.4mm. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. |
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