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IDT7223611L15PQF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7223611L15PQF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 20 page Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full ( AF) and Almost-Empty (AE) flags • Microprocessor Interface Control Logic • Full Flag ( FF) and Almost-Full (AF) flags synchronized by CLKA • Empty Flag ( EF) and Almost-Empty (AE) flags synchro- nized by CLKB • Passive parity checking on each Port • Parity Generation can be selected for each Port • Supports clock frequencies up to 67MHz COMMERCIAL TEMPERATURE RANGE MAY 1997 ©1997 Integrated Device Technology, Inc. DSC-3024/4 IDT723611 CMOS SyncFIFO 64 x 36 • Fast access times of 10ns • Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving 120-pin Thin Quad Flatpack (PF) • Low-power advanced CMOS technology • Industrial temperature range (-40oC to +85oC) is avail- able, tested to military elecrical specifications DESCRIPTION: The IDT723611 is a monolithic, high-speed, low-power, CMOS Synchronous (clocked) FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port A to Port B. The FIFO has flags to indicate empty and full conditions, and two programmable flags, Almost-Full ( AF) and Almost-Empty ( AE), to indicate when a selected number of words is stored in memory. Communication between each port can take place through two 36-bit mailbox registers. Each FUNCTIONAL BLOCK DIAGRAM Mail 2 Register Mail 1 Register Write Pointer Read Pointer Status Flag Logic CLKA CSA W/ RA ENA MBA Port-A Control Logic Reset Logic RST PEFA MBF2 CLKB CSB W/ RB ENB MBB Port-B Control Logic MBF1 EF AE 36 B0 - B35 FF AF FS0 FS1 3024 drw 01 Programmable Flag Offset Registers A0 - A35 Parity Gen/Check FIFO ODD/ EVEN PGA Parity Gen/Check PGB PEFB 36 64 x 36 SRAM • SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. 1 For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. |
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