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IDT723612L30PF Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT723612L30PF Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 29 page  11 COMMERCIAL TEMPERATURE RANGE IDT723612 BiCMOS SyncBiFIFO ™ 64 x 36 x 2 X or less words in memory and is HIGH when the FIFO contains (X+1) or more words. Two LOW-to-HIGH transitions of the almost-empty flag synchronizing clocks are required after a FIFO write for the almost-empty flag to reflect the new level of fill. Therefore, the almost-empty flag of a FIFO containing (X+1) or more words remains LOW if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An almost-empty flag is set HIGH by the second LOW- to-HIGH transition of the synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 6 and 7). ALMOST FULL FLAGS ( AFA AFA, AFB AFB) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an almost-full flag monitors a write-pointer and read- pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost- full state is defined by the value of the almost-full and almost- empty offset register (X). This register is loaded with one of four preset values during a device reset (see Reset above). An almost-full flag is LOW when the FIFO contains (64-X) or more words in memory and is HIGH when the FIFO contains [64-(X+1)] or less words. Two LOW-to-HIGH transitions of the almost-full flag synchronizing clock are required after a FIFO read for the almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [64-(X+1)]or less words remains LOW if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of words in memory to [64-(X+1)]. An almost-full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO read that reduces the number of words in memory to [64-(X+1)]. A second LOW-to-HIGH transition of an almost-full flag synchronizing clock begins the first syn- chronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [64- (X+1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 13 and 14). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and MBA HIGH. A LOW- to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and MBB is HIGH. Writing data to a mail register sets the corresponding flag ( MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When a port's data outputs are active, the data on the bus comes from the FIFO output register when the port mailbox- select input (MBA, MBB) is LOW and from the mail register when the port mailbox-select input is HIGH. The mail1 register flag ( MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and MBB is HIGH. The mail2 register flag ( MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when port-A read is selected by CSA, W/RA, and ENA and MBA is HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. PARITY CHECKING The port-A inputs (A0-A35) and port-B inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a LOW level on the port parity error flag ( PEFA, PEFB). Odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select input. A parity error on one or more bytes of a port is reported by a LOW level on the corresponding port parity error flag ( PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18- A26, and A27-A35 with the most significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9- B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. When odd/even parity is selected, a port parity error flag ( PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to the bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is se- lected for port-A reads (PGA = HIGH). When a port-A read from the mail2 register with parity generation is selected with W/ RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA HIGH, the port-A parity error flag ( PEFA) is held HIGH regard- less of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB = HIGH). When a port-B read from the mail1 register with parity generation is selected with W/ RB LOW, CSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH, the port- B parity error flag ( PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs. PARITY GENERATION A HIGH level on the port-A parity generate select (PGA) or port-B parity generate select (PGB) enables the IDT723612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-A8, A9-A17, A18- 26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9- B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all thirty-six inputs regard- less of the state of the parity generate select (PGA, PGB) |
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