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IDT723614L15PF Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT723614L15PF
Description  CMOS SyncBiFIFOO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
Download  39 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT723614L15PF Datasheet(HTML) 7 Page - Integrated Device Technology

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COMMERCIAL TEMPERATURE RANGE
IDT723614 CMOS SyncBiFIFO
™ WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
CSB
CSB
W/
RRB
ENB
SIZ1, SIZ0
CLKB
B0-B35 Outputs
Port Functions
H
X
X
X
X
In High-Impedance State
None
L
H
L
X
X
In High-Impedance State
None
L
H
H
One, both LOW
In High-Impedance State
FIFO2 Write
L
H
H
Both HIGH
In High-Impedance State
Mail2 Write
L
L
L
One, both LOW
X
Active, FIFO1 Output Register
None
L
L
H
One, both LOW
Active, FIFO1 Output Register
FIFO1 read
L
L
L
Both HIGH
X
Active, Mail1 Register
None
L
L
H
Both HIGH
Active, Mail1 Register
Mail1 Read (Set
MBF1 HIGH)
CSA
CSA
W/
RRA
ENA
MBA
CLKA
A0-A35 Outputs
Port Functions
H
X
X
X
X
In High-Impedance State
None
L
H
L
X
X
In High-Impedance State
None
LH
H
L
In High-Impedance State
FIFO1 Write
LH
H
H
In High-Impedance State
Mail1 Write
L
L
L
L
X
Active, FIFO2 Output Register
None
LL
H
L
Active, FIFO2 Output Register
FIFO2 Read
L
L
L
H
X
Active, Mail2 Register
None
LL
H
H
Active, Mail2 Register
Mail2 Read (Set
MBF2 HIGH)
ALMOST-FULL AND
FS1
FS0
RST
RST
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
HH
16
HL
12
LH
8
LL
4
clock that reads data from the FIFO have not elapsed since the
time the word was written. The empty flag of the FIFO is set
HIGH by the second LOW-to-HIGH transition of the synchro-
nizing clock, and the new data word can be read to the FIFO
output register in the following cycle.
A LOW-to-HIGH transition on an empty flag synchroniz-
ing clock begins the first synchronization cycle of a write if the
clock transition occurs at time tSKEW1 or greater after the write.
Otherwise, the subsequent clock cycle can be the first syn-
chronization cycle (see Figure 13 and 14).
TABLE 2: PORT-A ENABLE FUNCTION TABLE
TABLE 1: FLAG PROGRAMMING
TABLE 3: PORT-B ENABLE FUNCTION TABLE
FULL FLAG (
FFA
FFA, FFB
FFB)
The full flag of a FIFO is synchronized to the port clock
that writes data to its array. When the full flag is HIGH, a
memory location is free in the SRAM to receive new data. No
memory locations are free when the full flag is LOW and
attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is
incremented. The state machine that controls a full flag
monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous
memory location is ready to be written in a minimum of three
cycles of the full flag synchronizing clock. Therefore, a full flag
is LOW if less than two cycles of the full flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the full
flag synchronization clock after the read sets the full flag
HIGH and the data can be written in the following clock cycle.
A LOW-to-HIGH transition on a full flag synchronizing
clock begins the first synchronization cycle of a read if the
clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first syn-
chronization cycle (see Figure 15 and 16).


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