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IDT72264L15PF Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72264L15PF Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 31 page 7 IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO ™ (8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9) COMMERCIAL TEMPERATURE RANGES SIGNAL DESCRIPTIONS: INPUTS: DATA IN (D0 - D17) All 18 data inputs (D0 - D17) function when the Memory Array Configuration input (MAC) is tied to ground. Only 9-data inputs ( D0 - D8) function when MAC is connected to Vcc. The other data inputs (D9 - D17) do not function and may either be tied to ground or left open. CONTROLS: MEMORY ARRAY CONFIGURATION (MAC) The MAC line determines whether the FIFO will operate with a nine-bit-wide data bus or an 18-bit wide data bus. A FIFO is configured for 18-bit wide operation has half the memory depth of the same FIFO configured for 9-bit wide operation. MAC must be tied to either GND or Vcc. Connect- ing MAC to Vcc will configure the FIFO's input and output data buses to be 9 bits wide. In this case, the IDT72264 will have a 16384x 9 organization, and the IDT72274 will have a 32678 x 9 organization. Connecting MAC to GND will configure the FIFO's input and output data buses to be 18 bits wide. In this case, the IDT72264 will have a 8192 x 18 organization, and the IDT72274 will have a 16384 x 18 organization. MAC must be set before Master Reset; afterwards, it cannot be dynamically varied. MASTER RESET ( MRS MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH. If FWFT is LOW during Master Reset then the IDT Standard Mode, along with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT is HIGH, then the First Word Fall through Mode (FWFT), along with IR and OR, are selected. OR will go HIGH and IR will go LOW. If LD is LOW during Master Reset, then PAE is assigned a threshold 127 words from the empty boundary and PAF is assigned a threshold 127 words from the full boundary; 127 words corresponds to an offset value of 07FH. Following Master Reset, parallel loading of the offsets is permitted, but not serial loading. If LD is HIGH during Master Reset, then PAE is assigned a threshold 1023 words from the empty boundary and PAF is assigned a threshold 1023 words from the full boundary; 1023 words corresponds to an offset value of 3FFH. Following Master Reset, serial loading of the offsets is permitted, but not parallel loading. Regardless of whether serial or parallel offset loading has been selected, parallel reading of the registers is always permitted. (See section describing the LD line for further details). During a Master Reset, the output register is initialized to all zeroes. A Master Reset is required after power up, before a write operation can take place. MRS is asynchronous PARTIAL RESET ( PRS PRS) A Partial Reset is accomplished whenever the PRS input is taken to a LOW state. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH, and HF goes HIGH. Whichever mode is active at the time of partial reset, IDT Standard Mode or First Word Fall-through, that mode will remain selected. If the IDT Standard Mode is active, then FF will go HIGH and EF will go LOW. If the First word Fall-through Mode is active, then OR will go HIGH, and IR will go LOW. Following Partial Reset, all values held in the offset regis- ters remain unchanged. The programming method (parallel or serial) currently active at the time of Partial Reset is also retained. The output register is initialized to all zeroes. PRS is asynchronous. A Partial Reset is useful for resetting the device during the course of operation, when reprogramming flag settings may not be convenient. RETRANSMIT ( RT RT) The Retransmit operation allows data that has already been read to be accessed again. There are two stages: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of memory. Retransmit Setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. At least one word, but no more than Full - 2 words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit Setup. (For the IDT72264, 8,192 when MAC is LOW, 16,384 when MAC is HIGH; For the IDT72274, Full = 16,384 words when MAC is LOW, 32,768 when MAC is LOW). If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit Setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes HIGH, Retransmit Setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard Mode is selected, every word read including the first word following Retransmit Setup re- quires a LOW on REN to enable the rising edge of RCLK. Writing operations can begin after one of two conditions have been met: EF is HIGH or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the RT pulse. The deassertion time of EF during Retransmit Setup is variable. The parameter tRTF1, which is measured from the rising RCLK edge enabled by RT to the rising edge of EF is described by the following equation: tRTF1 max. = 14*Tf + 3*TRCLK (in ns) where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period. |
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