IDT723611 CMOS SyncFIFO

™

64 x 36

COMMERCIAL TEMPERATURE RANGES

7

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND

OPERATING FREE-AIR TEMPERATURES

IDT723611L15 IDT723611L20 IDT723611L30

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA or CLKB

–

66.7

–

50

–

33.4

Mhz

Clock Cycle Time, CLKA or CLKB

15

–

20

–

30

–

Mhz

Pulse Duration, CLKA or CLKB HIGH

6–8–

12

–

ns

Pulse Duration, CLKA or CLKB LOW

6–8–

12

–

ns

Setup Time, A0-A35 before CLKA

↑ and B0-B35

4–5–6

–

ns

before CLKB

↑

CSA, W/RA, before CLKA↑; CSB, W/RB before

6–6–7

–

ns

CLKB

↑

ENA before CLKA

↑; ENB before CLKB↑

4–5–6

–

ns

MBA before CLKA

↑; ENB before CLKB↑

4–5–6

–

ns

Setup Time, ODD/

EVEN and PGB before

4–5–6

–

ns

CLKB

Setup Time,

RST LOW before CLKA↑

5–6–7

–

ns

or CLKB

Setup Time, FS0 and FS1 before

RST HIGH

5–6–7

–

ns

Hold Time, A0-A35 after CLKA

↑ and B0-B35

1–1–1

–

ns

after CLKB

↑

CSA, W/RA after CLKA↑; CSB, W/RB

1–1–1

–

ns

after CLKB

↑

ENA after CLKA

↑; ENB after CLKB↑

111

ns

MBA after CLKA

↑; MBB after CLKB↑

111

ns

Hold TIme, ODD/

0–0–0

–

ns

Hold Time,

6–6–7

–

ns

Hold Time, FS0 and FS1 after

RST HIGH

4–4–4

–

ns

↑ and CLKB↑

8–8–

10

–

ns

for

EF, FF

↑ and CLKB↑

9–

16

–

20

–

ns

for

AE, AF

Notes:

1.

Only applies for a rising edge of CLKB that does a FIFO read.

2.

Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3.

Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relation-

ship between CLKA cycle and CLKB cycle.