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IDT723622L15PF Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT723622L15PF Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 26 page 5.22 8 IDT723622/723632/723642 CMOS SyncBiFIFO ™ 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE 723622-15 723622-20 723622-30 723632-15 723632-20 723632-30 723642-15 723642-20 723642-30 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB 66.7 50 33.4 MHz tCLK Clock Cycle Time, CLKA or CLKB 15 20 30 ns tCLKH Pulse Duration, CLKA or CLKB HIGH 6 8 10 ns tCLKL Pulse Duration, CLKA and CLKB LOW 6 8 10 ns tDS Setup Time, A0-A35 before CLKA ↑ and B0-B35 4 5 6 ns before CLKB ↑ tENS Setup Time, CSA, W/RA, ENA, and MBA before 4.5 5 6 ns CLKA ↑; CSB, W/RB, ENB, and MBB before CLKB↑ tRSTS Setup Time, RST1 or RST2 LOW before CLKA↑ 56 7 ns or CLKB ↑(1) tFSS Setup Time, FS0 and FS1 before RST1 and RST2 7.5 8.5 9.5 ns HIGH tDH Hold Time, A0-A35 after CLKA ↑ and B0-B35 after 1 1 1 ns CLKB ↑ tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;1 1 1 ns CSB, W/RB, ENB, and MBB after CLKB↑ tRSTH Hold Time, RST1 or RST2 LOW after CLKA↑ or 4 4 5 ns CLKB ↑(1) tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 3 3 ns tSKEW1(2) Skew Time, between CLKA ↑ and CLKB↑ for ORA, 7.5 9 11 ns ORB, IRA, and IRB tSKEW2(2) Skew Time, between CLKA ↑ and CLKB↑ for AEA, 121620 ns AEB, AFA, and AFB NOTES: 1. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPER- ATING FREE-AIR TEMPERATURE |
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