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IDT72402 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72402 Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 9 page IDT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES 5.01 5 Data Output Data is shifted out on the HlGH-to-LOW transition of Shift Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and Output Ready (OR) will go HIGH. If data is not present, Output Ready will stay LOW indicating the FIFO is empty. The last valid word read from the FIFO will remain at the FlFOs output when it is empty. When the FIFO is not empty, Output Ready (OR) goes LOW on the LOW-to-HIGH transition of Shift Out. Previous data remains on the output until the HIGH-to-LOW transition of Shift Out (SO). Fall-Through Mode The FIFO operates in a fall-through mode when data gets shifted into an empty FIFO. After a fall-through delay the data propagates to the output. When the data reaches the output, the Output Ready (OR) goes HIGH. Fall-through mode also occurs when the FIFO is completely full. When data is shifted out of the full FIFO, a location is available for new data. After a fall-through delay, the Input Ready goes HIGH. If Shift In is HIGH, the new data can be written to the FIFO. Since these FlFOs are based on an internal dual-port RAM architecture with separate read and write pointers, the fall- through time (tPT) is one cycle long. A word may be written into the FIFO on a clock cycle and can be accessed on the next clock cycle. TIMING DIAGRAMS 2747 drw 07 SHIFT IN INPUT DATA INPUT READY tSIH 1/fIN t SIL 1/fIN tIRH tIRL tIDS tIDH Figure 2. Input Timing 2747 drw 08 SHIFT IN INPUT DATA INPUT READY STABLE DATA (1) (2) (3) (4) (5) (6) Figure 3. The Mechanism of Shifting Data Into the FIFO NOTES: 1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied. 2. Input Data is loaded into the first word. 3. Input Ready goes LOW indicating the first word is full. 4. The write pointer is incremented. 5. The FIFO is ready for the next word. 6. If the FIFO is full then the Input Ready remains LOW. 7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4). (7) |
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