Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

©1996 Integrated Device Technology, Inc.

DSC-2748/7

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IDT72413

CMOS PARALLEL

64 x 5-BIT FIFO

WITH FLAGS

FEATURES:

•

First-ln/First-Out Dual-Port memory—45MHz

•

64 x 5 organization

•

Low-power consumption

— Active: 200mW (typical)

•

RAM-based internal structure allows for fast fall-through

time

•

Asynchronous and simultaneous read and write

•

Expandable by bit width

•

Cascadable by word depth

•

Half-Full and Almost-Full/Empty status flags

•

IDT72413 is pin and functionally compatible with the

MMI67413

•

High-speed data communications applications

•

Bidirectional and rate buffer applications

•

High-performance CMOS technology

•

Available in plastic DIP, CERDIP and SOIC

•

Military product compliant to MIL-STD-883, Class B

•

able, tested to military electrical specifications

DESCRIPTION:

The IDT72413 is a 64 x 5, high-speed First-In/First-Out

(FIFO) that loads and empties data on a first-in-first-out basis.

It is expandable in bit width. All speed versions are cascad-

able in depth.

The FIFO has a Half-Full Flag, which signals when it has 32

or more words in memory. The Almost-Full/Empty Flag is

active when there are 56 or more words in memory or when

there are 8 or less words in memory.

The IDT72413 is pin and functionally compatible to the

MMI67413. It operates at a shift rate of 45MHz. This makes it

ideal for use in high-speed data buffering applications. The

IDT72413 can be used as a rate buffer, between two digital

systems of varying data rates, in high-speed tape drivers, hard

disk controllers, data communications controllers and

graphics controllers.

The IDT72413 is fabricated using IDTs high-performance

CMOS process. This process maintains the speed and high

output drive capability of TTL circuits in low-power CMOS.

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

2748 drw 01

FIFO

INPUT

STAGE

64 x 5

MEMORY

ARRAY

FIFO

OUTPUT

STAGE

INPUT

CONTROL

LOGIC

REGISTER

CONTROL

LOGIC

OUTPUT

CONTROL

LOGIC

FLAG

CONTROL

LOGIC

)

(MR)

MASTER

RESET

INPUT

READY

SHIFT

IN

(IR)

(SI)

SHIFT

OUT

OUPUT

READY

(SO)

(OR)

OUPUT ENABLE

(OE)

HALF-FULL (HF)

ALMOST-FULL/

EMPTY (AF/E)

The IDT logo is a registered trademark of Integrated Device Technology,Inc.

FAST is a trademark of National Semiconductor, Inc.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.