5.02

10

IDT72413

CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

APPLICATIONS

2748 drw 16

SYSTEM 1

ENBL SI

TWO

IDT72413

64 x 8

OR

SO

IR

SI

8-BITS

8-BITS

SYSTEM 2

IO RDY

ALMOST-FULL/

EMPTY

HALF-FULL FLAG

INTERRUPT

INTERRUPT

NOTE:

1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.

Figure 14. Application for IDT72413 for Two Asynchronous Systems

2748 drw 15

IR

SI

SO

OR

MR

COMPOSITE

OUTPUT

READY

SHIFT IN

COMPOSITE

INPUT

READY

HF

AF/E

OE

IR

SI

SO

OR

MR

HF

AF/E

OE

IR

SI

SO

OR

MR

HF

AF/E

OE

OUTPUT

ENABLE

MASTER

RESET

SHIFT OUT

NOTE:

1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready

flags. This requirement is due to the different fall-through times of the FIFOs.

Figure 13. 64 x 15 FIFO with IDT72413