 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT72274L20PF Datasheet(PDF) 3 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT72274L20PF Datasheet(HTML) 3 Page - Integrated Device Technology |
|
|
3 / 31 page  3 IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO ™ (8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9) COMMERCIAL TEMPERATURE RANGES In the serial method, SEN together with LD are used to load the offset registers via the Serial Input (SI). In the parallel method, WEN together with LD can be used to load the offset registers via Dn. REN together with LD can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading is selected. During Master Reset ( MRS), the read and write pointers are set to the first location of the FIFO. The FWFT line selects IDT Standard Mode or FWFT Mode. The LD pin selects one of two partial flag default settings (127 or 1023) and, also, serial or parallel programming. The flags are updated accordingly. The Partial Reset ( PRS) also sets the read and write pointers to the first location of the memory. However, the mode setting, programming method, and partial flag offsets are not altered. The flags are updated accordingly. PRS is useful for resetting a device in mid-operation, when repro- gramming offset registers may not be convenient. The Retransmit function allows the read pointer to be reset to the first location in the RAM array. It is synchronized to RCLK when RT is LOW. This feature is convenient for sending the same data more than once. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. This occurs if neither a read nor a write occurs within 10 cycles of the faster clock, RCLK or WCLK. During the Power Down state, supply current consumption (ICC2) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power Down state. The IDT72264/72274 are depth expandable. The addition of external components is unnecessary. The IR and OR functions, together with REN and WEN, are used to extend the total FIFO memory capacity. The FS line ensures optimal data flow through the FIFO. It is tied to GND if the RCLK frequency is higher than the WCLK frequency or to Vcc if the RCLK frequency is lower than the WCLK frequency The IDT72264/72274 is fabricated using IDT’s high speed submicron CMOS technology. NOTES : 1. When the data path is selected to be 9 bits wide (MAC is HIGH), D9 - D17 may be tied to ground or left open, Q9 - Q17 must be left open. 2. DNC = Do not connect D8 Pin 1 Designator AB C D EF G H J K L Q0 D2 PAF DNC VCC RCLK REN OE GND DNC MRS LD WCLK PRS VCC WEN D17 MAC D15 D16 D11 D14 D12 D10 D9 D7 D6 PAE D4 D3 D1 D0 Q1 Q2 GND Q3 Q4 GND Q8 Q7 Q10 DNC GND VCC Q17 Q16 Q15 Q14 Q13 Q12 Q9 HF EF/ OR FF/ IR 11 10 09 08 07 06 05 04 03 02 01 RT FWFT/ SI D13 D5 GND VCC GND Q11 Q6 Q5 3218 drw 03 SEN FS GND PGA (G68-1, order code: G) TOP VIEW PIN CONFIGURATIONS (CONT.) |
Similar Part No. - IDT72274L20PF |
|
Similar Description - IDT72274L20PF |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
