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IDT71V421L35TF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V421L35TF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 14 page ©2001 Integrated Device Technology, Inc. AUGUST 2001 DSC-3026/8 1 HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS IDT71V321S/L IDT71V421S/L .eatures x x x x x High-speed access – Commercial: 25/35/55ns (max.) – Industrial: 25ns (max.) x x x x x Low-power operation – IDT71V321/IDT71V421S — Active: 325mW (typ.) — Standby: 5mW (typ.) – IDT71V321/V421L — Active: 325mW (typ.) — Standby: 1mW (typ.) x x x x x Two INT flags for port-to-port communications .unctional Block Diagram NOTES: 1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input. 2. BUSY and INT are totem-pole outputs. x x x x x MASTER IDT71V321 easily expands data bus width to 16- or-more-bits using SLAVE IDT71V421 x x x x x On-chip port arbitration logic (IDT71V321 only) x x x x x BUSY output flag on IDT71V321; BUSY input on IDT71V421 x x x x x Fully asynchronous operation from either port x x x x x Battery backup operation—2V data retention (L only) x x x x x TTL-compatible, single 3.3V power supply x x x x x Available in 52-pin PLCC, 64-pin TQFP and STQFP packages x x x x x Industrial temperature range (–40°C to +85°C) is available for selected speeds I/O Control Address Decoder MEMORY ARRAY ARBITRATION and INTERRUPT LOGIC Address Decoder I/O Control R/ WL CEL OEL BUSYL A10L A0L 3026 drw 01 I/O0L-I/O7L CEL OEL R/ WL INTL BUSYR I/O0R-I/O7R A10R A0R INTR CER OER (2) (1,2) (1,2) (2) R/ WR CER OER 11 11 R/ WR |
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