5

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723613 CMOS CLOCKED FIFO WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36

Symbol

Name

I/O

Description

PGA

Port A Parity Generation

I

Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity

generated is selected by the state of the ODD/

PGB

Port B Parity

I

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is

selected by the state of the ODD/

RST

Reset

I

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB

must occur while

RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF

flags LOW. The LOW-to-HIGH transition of

Almost-Full flag and Almost-Empty flag offset.

SIZ0,

Port B Bus Size Selects

I

A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and

BE, and the following LOW-to

SIZ1

(Port B)

HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be

long word, word, or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit

write or read.

SW0,

Port B Byte Swap Selects

I

At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by

SW1

(Port B)

SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte order

swapping is possible with any bus-size selection.

W/

RA

Port A Write/Read Select

I

A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH

Select

RA is HIGH.

W/

RB

Port B Write/Read Select

I

A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH

RB is HIGH.

PIN DESCRIPTION (CONTINUED)