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IDT72521L35G Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72521L35G Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 28 page IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES 5.32 11 Bit Function 0 Select Port B Interface 0 Pins are RB and WB (Intel-style interface) RB and WB or DSB and R/WB 1 Pins are DSB and R/WB (Motorola-style interface) 1 Unused 2 Full Flag Definition 0 Write pointer meets read pointer 1 Write pointer meets reread pointer 3 Empty Flag Definition 0 Read pointer meets write pointer 1 Read pointer meets rewrite pointer 4 REQ Pin Polarity 0 REQ pin active HIGH 1 REQ pin active LOW 5 ACK Pin Polarity 0 ACK pin active LOW 1 ACK pin active HIGH 7-6 REQ / ACK Timing 00 2 internal clocks between REQ assertion and ACK assertion 01 3 internal clocks between REQ assertion and ACK assertion 10 4 internal clocks between REQ assertion and ACK assertion 11 5 internal clocks between REQ assertion and ACK assertion 8 Port B Read & Write 0 RB, WB, and DSB are asserted for 1 internal clock Timing Control for Peripheral Mode 1 RB, WB, and DSB are asserted for 2 internal clocks 9 Internal Clock 0 Internal clock = CLK Frequency Control 1 Internal clock = CLK divided by 2 10 Port B Interface 0 Processor interface mode (Port B controls are inputs) Mode Control 1 Peripheral interface mode (Port B controls are outputs) 11 Unused 12 Unused 13 Unused 14 Unused 15 Unused CONFIGURATION REGISTER 5 FORMAT 15 6 5 4 3 2 1 0 Unused PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 2668 tbl 13 Figure 4. BiFIFO Configuration Register 6 Format for Programmable I/O Data CONFIGURATION REGISTER 7 FORMAT 2668 tbl 14 Figure 5. BiFIFO Configuration Register 7 Format for Programmable I/O Direction Mask Unused MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 15 6 5 4 3 2 1 0 2668 tbl 12 Table 10. BiFIFO Configuration Register 5 Format CONFIGURATION REGISTER 6 FORMAT |
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