6.02

9

IDT7132SA/LA AND IDT7142SA/LA

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2692 drw 12

R/

R/

(2)

(1)

TIMING WAVEFORM OF WRITE WITH

BUSY

BUSY

BUSY

BUSY

NOTES:

BUSY Input (IDT7142, slave) or Output (IDT7132, master).

2.

BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.

3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

CE

CE

CE

CE

ADDR

'A'

ADDRESSES MATCH

2692 drw 13

(2)

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

2692 drw 14

(2)

NOTES:

1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.

BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).