IDT72413L35PB datasheet(5/11 Pages) IDT

Part #	IDT72413L35PB

Description	CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

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Manufacturer	IDT [Integrated Device Technology]

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5 / 11 page

IDT72413

CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

5.02

5

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 1

2748 tbl 07

circuit

*Including scope and jig

DATA OUTPUT

Data is shifted out on the HIGH-to-LOW transition of Shift

Out (SO). This causes the internal read pointer to be ad-

vanced to the next word location. If data is present, valid data

will appear on the outputs and Output Ready (OR) will go

HIGH. If data is not present, Output Ready will stay LOW

indicating the FIFO is empty. The last valid word read from the

FIFO will remain at the FlFOs output when it is empty. When

the FIFO is not empty Output Ready (OR) goes LOW on the

LOW-to-HlGH transition of Shift Out.

FALL-THROUGH MODE

The FIFO operates in a Fall-Through Mode when data gets

shifted into an empty FIFO. After the fall-through delay the

data propagates to the output. When the data reaches the

output, the Output Ready (OR) goes HIGH.

A Fall-Through Mode also occurs when the FIFO is

completely full. When data is shifted out of the full FIFO a

location is available for new data. After a fall-through delay,

the lnput Ready goes HlGH. If Shift In is HIGH, the new data

can be written to the FIFO. The fall-through delay of a RAM-

based FIFO (one clock cycle) is far less than the delay of a

Shift register-based FIFO.

FUNCTIONAL DESCRIPTION:

The IDT72413, 65 x 5 FIFO is designed using a dual-port

RAM architecture as opposed to the traditional shift register

approach. This FIFO architecture has a write pointer, a read

pointer and control logic, which allow simultaneous read and

write operations. The write pointer is incremented by the

falling edge of the Shift In (Sl) control; the read pointer is

incremented by the falling edge of the Shift Out (SO). The

Input Ready (IR) signals when the FIFO has an available

memory location; Output Ready (OR) signals when there is

valid data on the output. Output Enable (OE) provides the

capability of three-stating the FIFO outputs.

FIFO RESET

The FIFO must be reset upon power up using the Master

Reset (MR) signal. This causes the FIFO to enter an empty

state signified by Output Ready (OR) being LOW and Input

Ready (IR) being HIGH. In this state, the data outputs (Q0-4)

will be LOW.

DATA INPUT

Data is shifted in on the LOW-to-HIGH transition of Shift In

(Sl). This loads input data into the first word location of the

FIFO and causes the lnput Ready to go LOW. On the HlGH-

to-LOW transition of Shift In, the write pointer is moved to the

next word position and Input Ready (lR) goes HlGH indicating

the readiness to accept new data. If the FIFO is full, Input

Ready will remain LOW until a word of data is shifted out.

RESISTOR VALUES FOR

STANDARD TEST LOAD

IOL

R1

R2

24mA

200

Ω

300

Ω

12mA

390

Ω

760

Ω

8mA

600

Ω

1200

Ω

Figure 1. Output Load

2748 tbl 08

R1

30pF*

R2

5V

TEST POINT

2748 drw 03

or equivalent

2K

Ω

30pF*

5V

OUTPUT

STANDARD TEST LOAD

DESIGN TEST LOAD

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