8

IDT723631/723641/723651 CMOS SyncFIFO

™

512 x 36, 1024 x 36, 2048 x 36

COMMERCIAL TEMPERATURE RANGE

IDT723631L15 IDT723631L20 IDT723631L30

IDT723641L15 IDT723641L20 IDT723641L30

IDT723651L15 IDT723651L20 IDT723651L30

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA or CLKB

–

66.7

–

50

–

33.4

MHz

Access Time, CLKB

↑ to B0-B35

3

11

3

13

3

15

ns

Propagation Delay Time, CLKA

↑ to IR

1

8

1

10

1

12

ns

Propagation Delay Time, CLKB

↑ to OR

1

8

1

10

1

12

ns

Propagation Delay Time, CLKB

↑ to AE

18

1

10

1

12

ns

Propagation Delay Time, CLKA

↑ to AF

18

1

10

1

12

ns

Propagation Delay Time, CLKA

↑ to MBF1

08

0

10

0

12

ns

LOW or

MBF2 HIGH and CLKB↑ to MBF2

LOW or

MBF1 HIGH

Propagation Delay Time, CLKA

3

13.5

3

15

3

17

ns

and CLKB

Propagation Delay Time, MBB to B0-B35 Valid

3

13

3

15

3

17

ns

Propagation Delay Time,

RST LOW to AE LOW

115

1

20

130

ns

and

AF HIGH

Enable Time,

CSA and W/RA LOW to A0-A35

2

12

2

13

2

14

ns

Active and

CSB LOW and W/RB HIGH to

B0-B35 Active

Disable Time,

CSA or W/RA HIGH to A0-A35

1

8

1

10

1

11

ns

at high impedance and

CSB HIGH or W/RB

LOW to B0-B35 at high impedance

AC ELECTRICAL CHARACTERISTICS

NOTES:

1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.

2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.

3023 tbl 07