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IDT723632L20PQF Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT723632L20PQF Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 26 page  5.22 11 IDT723622/723632/723642 CMOS SyncBiFIFO ™ 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CSA CSA W/ RRA ENA MBA CLKA A0-A35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None LH H L ↑ In high-impedance state FIFO1 write LH H H ↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None LL H L ↑ Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None LL H H ↑ Active, mail2 register Mail2 read (set MBF2 HIGH) CSB CSB W W/RB ENB MBB CLKB B0-B35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L L L X X In high-impedance state None LL H L ↑ In high-impedance state FIFO2 write LL H H ↑ In high-impedance state Mail2 write L H L L X Active, FIFO1 output register None LH H L ↑ Active, FIFO1 output register FIFO1 read L H L H X Active, mail1 register None LH H H ↑ Active, mail1 register Mail1 read (set MBF1 HIGH) Table 3. Port-B Enable Function Table Table 2. Port-A Enable Functlon Table port-B operation. The port-B control signals are identical to those of port A with the exception that the port-B write/read select ( W/RB) is the inverse of the port-A write/read select (W/ RA). The state of the port-B data (B0-B35) outputs is controlled by the port- B chip select ( CSB) and port-B write/read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reads and writes on port B are independent of any concurrent port-A operation. The setup and hold time constraints to the port clocks for the port chip selects and write/read selects are only for enabling write and read operations and are not related to high- impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s chip select and write/read select may change states during the setup and hold time window of the cycle. When a FIFO output-ready flag is LOW, the next data word is sent to the FIFO output register automatically by the LOW-to-HIGH transition of the port clock that sets the output- ready flag HIGH. When the output-ready flag is HIGH, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port’s chip select, write/ read select, enable, and mailbox select. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one an- other. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIF02. |
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