IDT72251L15J datasheet(4/14 Pages) IDT

Part #	IDT72251L15J

Description	CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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4 / 14 page

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

4



Figure 1. Output Load

*includes jig and scope capacitances

or equivalent circuit

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0

°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)

Commercial

Com'l & Ind'l(1)

IDT72421L10

IDT72421L15

IDT72421L25

IDT72201L10

IDT72201L15

IDT72201L25

IDT72211L10

IDT72211L15

IDT72211L25

IDT72221L10

IDT72221L15

IDT72221L25

IDT72231L10

IDT72231L15

IDT72231L25

IDT72241L10

IDT72241L15

IDT72241L25

IDT72251L10

IDT72251L15

IDT72251L25

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fS

Clock Cycle Frequency

—

100

—

66.7

—

40

MHz

tA

Data Access Time

2

6.5

2

10

2

15

ns

tCLK

Clock Cycle Time

10

—

15

—

25

—

ns

tCLKH

Clock High Time

4.5

—

6

—

10

—

ns

tCLKL

Clock Low Time

4.5

—

6

—

10

—

ns

tDS

Data Setup Time

3

—

4

—

6

—

ns

tDH

Data Hold Time

0.5

—

1

—

1

—

ns

tENS

Enable Setup Time

3

—

4

—

6

—

ns

tENH

Enable Hold Time

0.5

—

1

—

1

—

ns

tRS

ResetPulseWidth(2)

10

—

15

—

15

—

ns

tRSS

Reset Setup Time

8

—

10

—

15

—

ns

tRSR

Reset Recovery Time

8

—

10

—

15

—

ns

tRSF

Reset to Flag and Output Time

—

10

—

15

—

25

ns

tOLZ

Output Enable to Output in Low-Z(3)

0—

0

—

0

—

ns

tOE

Output Enable to Output Valid

3

6

3

8

3

13

ns

tOHZ

Output Enable to Output in High-Z(3)

36

3

8

3

13

ns

tWFF

Write Clock to Full Flag

—

6.5

—

10

—

15

ns

tREF

Read Clock to Empty Flag

—

6.5

—

10

—

15

ns

tPAF

Write Clock to Programmable Almost-Full Flag

—

6.5

—

10

—

15

ns

tPAE

Read Clock to Programmable Almost-Empty Flag

—

6.5

—

10

—

15

ns

tSKEW1

Skew time between Read Clock & Write Clock for

5

—

6

—

10

—

ns

Empty Flag & Full Flag

tSKEW2

Skew time between Read Clock & Write Clock for

14

—

15

—

18

—

ns

Almost-Empty Flag & Programmable Almost-Full Flag

NOTES:

1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

In Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 1

CAPACITANCE (Ta = +25

°C, f = 1.0MHz)

Symbol

Parameter

Conditions

Max.

Unit

CIN(2)

InputCapacitance

VIN = 0V

10

pF

COUT

(1,2)

OutputCapacitance

VOUT = 0V

10

pF

30pF*

1.1K

5V

680

Ω

D.U.T.

2655 drw 03

NOTES:

1. With output deselected (OE

≥ VIH).

2. Characterized values, not currently tested.

AC TEST CONDITIONS

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