7

IDT72V801/72V811/72V821/72V831/72V841/72V851

COMMERCIALANDINDUSTRIALTEMPERATURERANGE

Figure 3. Offset Register Formats and Default Values for the A and B FIFOs

contains four 8-bit offset registers which can be loaded with data on the inputs,

or read on the outputs. See Figure 3 for details of the size of the registers and

the default values.

If FIFO A (B) is configured to have programmable flags, when the

WENA1

(

WENB1) and WENA2/LDA(WENB2/LDB) are set LOW, data on the DA (DB)

inputsarewrittenintotheEmpty(LeastSignificantBit)Offsetregisteronthefirst

LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the

Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH

transitionofWCLKA(WCLKB),intotheFull(LeastSignificantBit)Offsetregister

on the third transition, and into the Full (Most Significant Bit) Offset register on

thefourthtransition. ThefifthtransitionofWCLKA(WCLKB)againwritestothe

Empty (Least Significant Bit) Offset register.

87

0

Empty Offset (LSB) Reg.

Default Value 007H

80

Full Offset (LSB) Reg.

Default Value 007H

7

80

Empty Offset (LSB)

Default Value 007H

80

Full Offset (LSB)

Default Value 007H

72V801 - 256 x 9 x 2

72V811 - 512 x 9 x 2

7

7

80

(MSB)

1

0

0

87

0

Empty Offset (LSB) Reg.

Default Value 007H

80

Full Offset (LSB) Reg.

Default Value 007H

7

80

Empty Offset (LSB)

Default Value 007H

80

Full Offset (LSB)

Default Value 007H

72V831 - 2,048 x 9 x 2

7

7

80

80

(MSB)

0000

2

(MSB)

000

3

80

80

(MSB)

0000

2

(MSB)

000

3

80

8

0

80

(MSB)

1

0

87

0

Empty Offset (LSB) Reg.

Default Value 007H

80

Full Offset (LSB) Reg.

Default Value 007H

7

72V821 - 1,024 x 9 x 2

80

(MSB)

00

1

80

(MSB)

00

1

4093 drw 05

72V841 - 4,096 x 9 x 2

80

Empty Offset (LSB)

Default Value 007H

80

Full Offset (LSB)

Default Value 007H

7

7

80

(MSB)

00000

4

72V851 - 8,192 x 9 x 2

(MSB)

00000

80

4

However,writingalloffsetregistersdoesnothavetooccuratonetime. One

or two offset registers can be written and then by bringing

LDA(LDB) HIGH,

FIFO A (B) is returned to normal read/write operation. When

LDA(LDB) is set

LOW, and

WENA1(WENB1) is LOW, the next offset register in sequence is

written.

ThecontentsoftheoffsetregisterscanbereadontheQA(QB)outputswhen

WENA2/

LDA (WENB2/LDB) is set LOW and both Read Enables RENA1,

RENA2(RENB1,RENB2)aresetLOW. DatacanbereadontheLOW-to-HIGH

transition of the Read Clock RCLKA (RCLKB).

A read and write should not be performed simultaneously to the offset

registers.