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IDT73720PQF Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT73720PQF Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 8 page IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE 11.5 7 SWITCH POSITION Test Switch Disable LOW Closed Enable LOW All Other Tests Open DEFINITIONS: 2527 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. TEST CIRCUITS AND WAVEFORMS Figure 5. Test Circuit for all outputs Pulse Generator R T D.U.T. VCC VIN C L V OUT 50pF 500 Ω 500 Ω 7.0V 2527 drw 07 AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 5%, TA = 0° to +70°C) 73720A 73720 Symbol Parameter Test Conditions (1) Min. (2) Max. Min. (2) Max. Units tPLH X to Y & X to Z Latches enabled CL = 50pF 2.0 6.0 2.0 7.5 ns tPHL RL = 500 Ohms tPLH Y to X & Z to X Latches enabled 2.0 6.0 2.0 7.5 ns tPHL tPLH Latch Enable to Y & Z Port LEXY to Y 2.0 7.0 2.0 8.5 ns tPHL LEXZ to Z tPLH Latch Enable to X LEYX to X 2.0 7.0 2.0 8.5 ns tPHL LEZX to X tPLH Path to X Port Propagation Delay 2.0 7.0 2.0 8.5 ns tPHL tHZ Y & Z Port Disable Time (T/ R, PATH, OEU, OEL)(3) 2.0 8.5 2.0 9.5 ns tLZ tZH Y & Z Port Enable Time (T/ R, PATH, OEU, OEL)(3) 2.0 9.5 2.0 10.5 ns tZL tHZ X-Port DisableTime (T/ R, OEU, OEL)(3) 2.0 8.5 2.0 9.5 ns tLZ tZH X-Port Enable Time (T/ R, OEU, OEL)(3) 2.0 9.5 2.0 10.5 ns tZL tSU Port to LE Set-up time 2.0 — 2.0 — ns tH Port to LE Hold time 1.5 — 1.5 — ns tW LE Pulse Width, HIGH or LOW (2) 3— 4 — ns NOTES: 2527 tbl 07 1. All timings are referenced to 1.5 V. 2. Minimum Delay Times, Enable Times, Disable Times and Pulse Width are guaranteed by design, but not tested. 3. Bus turnaround times are guaranteed by design, but not tested. (T/ R enable/disable times). |
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