7.2

6

IDT71256 S/L

CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

± 10%, All Temperature Ranges)

71256S55

(1)

71256S70

(1)

71256S85

(1)

71256S100

(1,3)

71256L55

(1)

71256L70

(1)

71256L85

(1)

71256L100

(1,3)

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle

Read Cycle Time

55

—

70

—

85

—

100

—

ns

Address Access Time

—

55

—

70

—

85

—

100

ns

Chip Select Access Time

—

55

—

70

—

85

—

100

ns

(2)

Chip Deselect to Output in Low-Z

5

—

5

—

5

—

5

—

ns

(2)

Output Enable to Output in Low-Z

—

25

—

30

—

35

—

40

ns

Output Enable to Output Valid

—

25

—

30

—

35

—

40

ns

(2)

Output Enable to Output in Low-Z

0

—

0

—

0

—

0

—

ns

(2)

Output Disable to Output in High-Z

0

25

0

30

—

35

—

40

ns

Output Hold from Address Change

5

—

5

—

5

—

5

—

ns

Write Cycle

Write Cycle Time

55

—

70

—

85

—

100

—

ns

Chip Select to End-of-Write

50

—

60

—

70

—

80

—

ns

Address Valid to End-of-Write

50

—

60

—

70

—

80

—

ns

Address Set-up Time

0

—

0

—

0

—

0

—

ns

Write Pulse Width

40

—

45

—

50

—

55

—

ns

Write Recovery Time

0

—

0

—

0

—

0

—

ns

Data to Write Time Overlap

25

—

30

—

35

—

40

—

ns

Data Hold from Write Time (

WE)0

—

0

—

0

—

0

—

ns

(2)

Write Enable to Output in High-Z

—

25

—

30

—

35

—

40

ns

(2)

Output Active from End-of-Write

5

—

5

—

5

—

5

—

ns

NOTES:

2946 tbl 11

1. –55

°C to +125°C temperature range only.

2. This parameter guaranteed by device characterization, but is not production tested.

3. Also available: 120 and 150 ns military devices.