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IDT71V321L55JI Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT71V321L55JI Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 14 page  6.42 IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 6 CE tACE tHZ tLZ tPD VALID DATA 50% OE DATAOUT CURRENT ICC ISS 50% 3026 drw 07 (4) (1) (1) (2) (2) (4) tLZ tHZ tAOE tPU Timing Waveform of Read Cycle No. 2, Either Side (3) NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/ W = VIH and the address is valid prior to or coincidental with CE transition LOW. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. Timing Waveform of Read Cycle No. 1, Either Side(1) NOTES: 1. R/ W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. ADDRESS DATAOUT tRC tOH PREVIOUS DATA VALID tAA tOH DATA VALID 3026 drw 06 tBDD (2,3) BUSYOUT |
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