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IDT74FCT16952ETPV Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT74FCT16952ETPV Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 8 page  IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER COMMERCIAL TEMPERATURE RANGE 11.5 4 ARCHITECTURE OVERVIEW The Bus Exchanger is used to service both read and write operations between the CPU and the dual memory busses. It includes independent data path elements for reads from and writes to each of the memory banks (Y and Z). Data flow control is managed by a simple set of control signals, analo- gous to a simple transceiver. In short, the Bus Exchanger allows bidirectional communication between ports X and Y and ports X and Z as illustrated in figure 1. The data path elements for each port include: Read Latch: Each of the memory ports Y and Z contains a transparent latch to capture the contents of the memory bus. Each latch features an independent latch enable. Write Latch: Each memory port Y and Z contains an indepen- dent latch to capture data from the CPU bus during writes. Each memory port write latch features an independent latch enable, allowing write data to be directed to a specific memory port without disrupting the other memory port. Data Flow Control Signals T/ RR (Transmit/Receive). This signal controls the direction of data transfer. A transmit is used for CPU writes, and a receive is used for read operations. OEU OEU, OEL OEL are the output enable control signals to select upper or lower bytes of all three ports. Path: The path control signal is used to select between the even memory path Y and the odd memory path Z during read or write operations. Path selects the memory port to be connected to the CPU bus (X-port), and is independent of the latch enable signals. Thus, it is possible to transfer data from one memory port to the CPU bus (X) while capturing data from the other memory port. MEMORY READ OPERATIONS Latch Mode In this mode the read operation consists of two stages. During the first stage, the data present at the memory port is captured by the read latch for that memory port. During a subsequent stage, data is brought from a selected memory port to the CPU A/D port X by using output enable control. The read operation is selected by driving T/ R LOW. The read is managed using the Path input to select the memory port (Y or Z); the LEYX/LEZX enable the data capture into the corresponding Read Latch. In this way, memory interleaving can be performed. While data from one bank is output onto the CPU bus, data on the other bank is captured in the other memory port. In the next cycle, the Path input is changed, enabling the next data element onto the CPU bus, while the first bank is presented with a new data element. Transparent Mode The Bus Exchanger may be used as a data transceiver by leaving all latches open or transparent. Memory Write Operations Memory write operations also consist of two distinct stages. During one stage, the write data is captured into the selected memory port write latch. During a later stage, the memory is presented on the memory port bus The write operation is selected by driving T/ R HIGH. Writes are thus performed using the Path input to select the memory port (Y or Z). The LEXY/LEXZ capture data in the correspond- ing Write Latch. Note that it is possible to utilize the bus exchanger’s write resources as an additional write buffer, if desired; the CPU A/D bus can be freed up once the data has been captured by the Bus Exchanger. APPLICATIONS Use as Part of the R3051 Family ChipSet Figure 2 shows the use of the Bus Exchanger in a typical R3051 based system. In write transactions, the R3051 drives data on the CPU bus. The latch enables are held open through the entire write; thus, the bus exchanger is used like a transceiver. The appropriate LEXY/LEXZ signal is derived from ALE (Logic LOW- indicating that the processor is driving data) and the low order address bit. The rising edge of Wr from the CPU, ends the write operation. During read transactions, the memory system is respon- sible for generating the input control signals to cause data to be captured at the memory ports. The memory controller is also responsible for acknowledging back to the CPU that the data is available, and causing the appropriate path to be selected. The R3721 DRAM controller for the R3051 family uses the transparent latches of the read ports. The R3721 directly controls the inputs of the bus exchanger, during both reads and writes. Consult the R3721 data sheet for more informa- tion on these control signals. Use in a general 32-bit System Figures 3 and 4 illustrate the use of the Bus Exchanger in a 32-bit microprocessor based system. Note the reduced pin count achieved with the Bus Exchanger. |
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