6.04

8

IDT7134SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W

W

W

W

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CE

CE

CE

CE

NOTES:

1. R/

W or CE must be High during all address transitions.

CE or R/W going High to the end-of-write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the

CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (

CE or R/W )is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output

Test Load (Figure 2).

8. If

OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

2720 drw 12

R/

W

ADDRESS

CE

1.20 in

CE

2720 drw 11

ADDRESS

R/

W

(4)

(4)

(2)

OE

(7)

(7)