Electronic Components Datasheet Search |
|
IDT72240L20TP Datasheet(PDF) 4 Page - Integrated Device Technology |
|
IDT72240L20TP Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 16 page 5.12 4 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO ™ 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Commercial Comm. & Mil. Comm. Comm/Mil 72200L12 72200L15 72200L20 72200L25 72200L35 72200L50 72210L12 72210L15 72210L20 72210L25 72210L35 72210L50 72420L12 72420L15 72420L20 72420L25 72420L35 72420L50 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min.Max. Unit fS Clock Cycle Frequency — 83.3 — 66.7 — 50 — 40 — 28.6 — 20 MHz tA Data Access Time 2 8 2 10 2 12 3 15 3 20 3 25 ns tCLK Clock Cycle Time 12 — 15 — 20 — 25 — 35 — 50 — ns tCLKH Clock High Time 5 — 6 — 8 — 10 — 14 — 20 — ns tCLKL Clock Low Time 5 — 6 — 8 — 10 — 14 — 20 — ns tDS Data Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns tDH Data Hold Time 0.5 — 1 — 1 — 1 — 2 — 2 — ns tENS Enable Set-up Time 3 — 4 — 5 — 6 — 8 — 10 — ns tENH Enable Hold Time 0.5 — 1 — 1 — 1 — 2 — 2 — ns tRS Reset Pulse Width(1) 12 — 15 — 20 — 25 — 35 — 50 — ns tRSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — 50 — ns tRSF Reset to Flag and Output Time — 12 — 15 — 20 — 25 — 35 — 50 ns tOLZ Output Enable to Output in Low-Z(2) 0— 0 — 0 — 0— 0— 0 — ns tOE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 3 28 ns tOHZ Output Enable to Output in High-Z(2) 3 7 3 8 3 10 3 13 3 15 3 28 ns tWFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tREF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tAF Write Clock to Almost-Full Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tAE Read Clock to Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 — 30 ns tSKEW1 Skew time between Read Clock & 5 — 6 — 8 — 10 — 12 — 15 — ns Write Clock for Empty Flag & Full Flag tSKEW2 Skew time between Read Clock & 22 — 28 — 35 — 40 — 42 — 45 — ns Write Clock for Almost-Empty Flag & Almost-Full Flag NOTES: 2680 tbl 07 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. |
Similar Part No. - IDT72240L20TP |
|
Similar Description - IDT72240L20TP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |