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IDT7132SA35L48 Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT7132SA35L48 Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 11 page  IDT7132SA/LA AND IDT7142SA/LA HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.02 6 AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5) 7132X20(2) 7132X25(6) 7132X35 7132X55 7132X100 7142X25(6) 7142X35 7142X55 7142X100 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time(3) 20 — 25 — 35 — 55 — 100 — ns tEW Chip Enable to End of Write 15 — 20 — 30 — 40 — 90 — ns tAW Address Valid to End of Write 15 — 20 — 30 — 40 — 90 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns tWP Write Pulse Width(4) 15 — 15 — 25 — 30 — 55 — ns tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns tDW Data Valid to End of Write 10 — 12 — 15 — 20 — 40 — ns tHZ Output High Z Time(1) — 10 — 10 — 15 — 25 — 40 ns tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns tWZ Write Enabled to Output in High Z(1) — 10 — 10 — 15 — 30 — 40 ns tOW Output Active From End of Write(1) 0— 0— 0— 0— 0 — ns TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE (3) CAPACITANCE(1) (TA = +25 °C,f = 1.0MHz) Symbol Parameter Conditions(2) Max. Unit CIN Input Capacitance VIN = 3dV 11 pF COUT Output Capacitance VIN = 3dV 11 pF NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 2692 tbl 10 CE tACE tHZ tLZ tPD VALID DATA tPU 50% OE DATAOUT CURRENT ICC ISS 50% 2692 drw 08 (4) (1) (1) (2) (2) (4) tLZ tHZ tAOE NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. R/ W = VIH, and the address is valid prior to or coincidental with CE transition Low. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. NOTES: 2692 tbl 09 1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. 0 °C to +70°C temperature range only, PLCC package only. 3. For Master/Slave combination, tWC = tBAA + tWP, since R/ W = VIL must occur after tBAA. 4. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 5. “X” in part numbers indicates power rating (SA or LA). 6. Not available in DIP packages. |
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