6.1

8

IDT7164S/L

CMOS STATIC RAM 64K (8K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WE

WE CONTROLLED TIMING)

(1, 2, 6)

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS

CS CONTROLLED TIMING)

(1, 2)

NOTES:

1.

2. A write occurs during the overlap of a LOW

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the

6.

OE is HIGH during a WE controlled write cycle, this requirement does not

7. Transition is measured

±200mV from steady state.

ADDRESS

2967 drw 08

WE

DATA VALID

(4)

(6)

2967 drw 09

ADDRESS

WE

DATA VALID

(5)