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IDT72261L10PFB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72261L10PFB Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 30 page  6 MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT72261/72271 SyncFIFO ™ 16,384 x 9, 32,768 x 9 Commercial Com'l & Mil. Commercial Military 72261L10 72261L12 72261L15 72261L20 72261L25 72271L10 72271L12 72271L15 72271L20 72271L25 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency — 100 — 83.3 — 66.7 — 50 — 40 MHz tA Data Access Time 2 8 2 9 2 10 2 12 3 15 ns tCLK Clock Cycle Time 10 — 12 — 15 — 20 — 25 — ns tCLKH Clock High Time 4.5 — 5 — 6 — 8 — 10 — ns tCLKL Clock Low Time 4.5(2) —5(2) —6(2) —8 — 10 — ns tDS Data Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns tDH Data Hold Time 0 — 0 — 1 — 1 — 1 — ns tENS Enable Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns tENH Enable Hold Time 0 — 0 — 1 — 1 — 1 — ns tLDS Load Set-up Time 3.5 — 3.5 — 4 — 5 — 6 — ns tLDH Load Hold Time 6.5 — 8.5 — 10 — 10 — 10 — ns tRS Reset Pulse Width(3) 10 — 12 — 15 — 20 — 25 — ns tRSS Reset Set-up Time 10 — 12 — 15 — 20 — 25 — ns tRSR Reset Recovery Time 10 — 12 — 15 — 20 — 25 — ns tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 20 — 25 ns tFWFT Mode Select Time 0 — 0 — 0 — 0 — 0 — ns tRTS Retransmit Set-Up Time 3.5 — 3.5 — 4 — 5 — 6 — ns tOLZ Output Enable to Output in Low Z(4) 0— 0— 0 — 0 — 0 — ns tOE Output Enable to Output Valid 3 7 3 7.5 3 8 3 10 3 13 ns tOHZ Output Enable to Output in High Z(4) 3 7 3 7.5 3 8 3 10 3 13 ns tWFF Write Clock to FF or IR —8 —9 — 10 — 12 — 15 ns tREF Read Clock to EF or OR —8 —9 — 10 — 12 — 15 ns tPAF Write Clock to PAF – 8 — 9 —10 — 12 —15 ns tPAE Read Clock to PAE —8 —9 — 10 — 12 — 15 ns tHF Clock to HF — 16 — 18 — 20 — 22 — 25 ns tSKEW1 Skew time between RCLK and WCLK 8 — 10 — 12 — 15 — 20 — ns for FF and IR tSKEW2 Skew time between RCLK and 15 — 18 — 21 — 25 — 35 — ns WCLK for PAE and PAF AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) 3097 tbl 06 NOTES: 1. All AC timings apply to both Standard IDT Mode and First Word Fall Through Mode. 2. For the RCLK line: tCLKL (min.) = 7 ns only when reading the offsets from the programmable flag registers; otherwise, use the table value. For the WCLK line, use the tCLKL (min.) value given in the table. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. 3097 tbl 08 1.5V Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V See Figure 1 1.5V 3ns AC TEST CONDITIONS Figure 1. Output Load * Includes jig and scope capacitances. 3036 drw 04 1.1K 30pF* 680 Ω 5V D.U.T. |
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