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IDT72521L35JB Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72521L35JB Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 28 page 5.32 10 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES CONFIGURATION REGISTER FORMATS 2668 tbl 11 Table 9. Configuration Register 4 Internal Flag Assignments to External Flag Pins Assignment Code Internal Flag Assigned to Flag Pin 0000 A →B Empty 0001 A →B Almost-Empty 0010 A →B Full 0011 A →B Almost-Full 0100 B →A Empty 0101 B →A Almost-Empty 0110 B →A Full 0111 B →A Almost-Full 1000 A →B Empty 1001 A →B Almost-Empty 1010 A →B Full 1011 A →B Almost-Full 1100 B →A Empty 1101 B →A Almost-Empty 1110 B →A Full 1111 B →A Almost-Full EXTERNAL FLAG ASSIGNMENT CODES Programmable Flags The IDT BiFIFO has eight internal flags. Associated with each FIFO memory array are four internal flags, Empty, Almost-Empty, Almost-Full and Full, for the total of eight internal flags. The Almost-Empty and Almost-Full offsets can be set to any depth through the Configuration Registers 0-3 (see Table 8). The flags are asserted at the depths shown in Table 11. After a hardware reset or a software Reset All, the almost flag offsets are set to 0. Even though the offsets are equivalent, the Empty and Almost-Empty flags have different timing which means that the flags are not coincident. Similarly, the Full and Almost-Full flags are not coincident after reset because of timing. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through Configuration Regis- ter 4 (see Table 9). For the specific flag timings, see Figures 20-23. The current state of all eight flags is available in the Status Register. Config. Reg. 0 Config. Reg. 1 Config. Reg. 2 Config. Reg. 3 Config. Reg. 4 Config. Reg. 5 Config. Reg. 6 Config. Reg. 7 X X X X X X X X X X X X X X X X X X X X X X X X A →B FIFO Almost Empty Flag Offset A →B FIFO Almost Full Flag Offset B →A FIFO Almost Empty Flag Offset B →A FIFO Almost Full Flag Offset Flag D Pin Assignment Flag C Pin Assignment Flag B Pin Assignment Flag A Pin Assignment General Control I/O Data I/O Direction Control 15 15 15 15 15 15 15 15 10 10 10 10 9 9 9 9 12 11 8 7 4 3 0 0 0 0 0 0 0 0 2668 drw 02 2668 tbl 10 NOTE: 1. Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT72511. Table 8. The BiFIFO Configuration Register Formats |
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