IDT54FCT138CD datasheet(1/6 Pages) IDT

Part #	IDT54FCT138CD

Description	FAST CMOS 1-OF-8 DECODER WITH ENABLE

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1992

7.3

DSC-4625/3

®

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST is a trademark of National Semiconductor Co.

FEATURES:

• IDT54/74FCT138 equivalent to FAST

™ speed

• IDT54/74FCT138A 35% faster than FAST

• IDT54/74FCT138C 40% faster than FAST

• Equivalent to FAST speeds output drive over full tem-

perature and voltage supply extremes

•IOL = 48mA (commercial) and 32mA (military)

• CMOS power levels (1mW typ. static)

• TTL input and output level compatible

• CMOS output level compatible

• Substantially lower input current levels than FAST

(5

µA max.)

• JEDEC standard pinout for DIP and LCC

• Product available in Radiation Tolerant and Radiation

Enhanced versions

• Military product compliant to MIL-STD-883, Class B

• Standard Military Drawing # 5962-87654 is listed on this

function. Refer to section 2.

DESCRIPTION:

The IDT54/74FCT138/A/C are 1-of-8 decoders built using

an advanced dual metal CMOS technology.

The IDT54/

74FCT138/A/C accept three binary weighted inputs (A0, A1,

A2) and, when enabled, provide eight mutually exclusive

active LOW outputs (

O0 - O7). The IDT54/74FCT138/A/C

feature three enable inputs, two active LOW (

E1, E2) and one

active HIGH (E3). All outputs will be HIGH unless

E1 and E2

are LOW and E3 is HIGH. This multiple enable function allows

easy parallel expansion of the device to a 1-of-32 (5 lines to

32 lines) decoder with just four IDT54/74FCT138/A/C devices

and one inverter.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP/SOIC/CERPACK

TOP VIEW

4

5

6

7

8

L20-2

18

17

16

15

14

INDEX

2581 drw 01

E3

NC

A2

E1

E2

O1

O2

O3

O4

9 10 11 12 13

32

1

20 19

LCC

TOP VIEW

IDT54/74FCT138

IDT54/74FCT138A

IDT54/74FCT138C

FAST CMOS

1-OF-8 DECODER

WITH ENABLE

2581 drw 02

O0

O1

O2

O3

O4

O5

O6

O7

E1 E2 E3

A0

A1

A2

5

6

7

8

A0

A1

1

2

3

4

16

15

14

13

12

11

10

9

Vcc

P16-1,

D16-1,

SO16-1

&

E16-1

A2

E1

E2

GND

O0

O1

O2

O3

O4

O

O6

O7

5

E3

1

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