5.5

6

IDT54/74FCT162H272AT/CT/ET

FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER

MILITARY AND COMMERCIAL TEMPERATURES RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

3071 tbl 10

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This parameter is guaranteed but not tested.

FCT162H272AT

FCT162H272CT

FCT162H272ET

Com'l.

Mil.

Com'l.

Mil.

Com'l.

Mil.

Symbol

Parameter

Propagation Delay

CLK to 1Bx or CLK to 2Bx

Ω

1.5

5.8

1.5

6.2

1.5

5.2

1.5

5.6

1.5

4.8

—

—

ns

Propagation

Delay

SEL Stable

CExB Enabled

1.5

6.0

1.5

6.4

1.5

5.4

1.5

5.8

1.5

5.0

—

—

ns

CLK to Ax

SEL Changing

CExB Disabled

1.5

6.0

1.5

6.4

1.5

5.4

1.5

5.8

1.5

5.4

—

—

ns

SEL Changing

CExB Enabled

1.5

7.6

1.5

7.9

1.5

6.6

1.5

7.0

1.5

5.6

—

—

ns

Output Enable Time

CLK to Ax, CLK to 1Bx, or

CLK to 2Bx

1.5

7.7

1.5

8.1

1.5

6.8

1.5

7.2

1.5

6.0

—

—

ns

Output Disable Time

CLK to Ax, CLK to 1Bx, or

CLK to 2Bx

1.5

6.4

1.5

6.8

1.5

6.0

1.5

6.4

1.5

5.6

—

—

ns

Set-Up Time, HIGH or LOW

Data to CLK

2.0

—

2.0

—

2.0

—

2.0

—

2.0

—

—

—

ns

Set-Up Time,

OEA to CLK,

OEB to CLK

2.0

—

2.0

—

2.0

—

2.0

—

2.0

—

—

—

ns

Set-Up Time, SEL to CLK

2.0

—

2.0

—

2.0

—

2.0

—

2.0

—

—

—

ns

Set-Up Time,

CEA1B to CLK,

CE1B to CLK, CE2B to CLK,

or

CEA2B to CLK

2.0

—

2.0

—

2.0

—

2.0

—

2.0

—

—

—

ns

Hold Time, CLK to Data

0

—

0

—

0

—

0

—

0

—

—

—

ns

Hold Time, CLK to

OEA,

CLK to

OEB, CLK to SEL

0.5

—

0.5

—

0.5

—

0.5

—

0.5

—

—

—

ns

Hold Time, CLK to

CEA1B,

CLK to

CE1B, CLK to CE2B,

CLK to

CEA2B

0—

0—

0—

0—

0—

—

—

ns

3.0

—

3.0

—

3.0

—

3.0

—

3.0

—

—

—

ns

—

0.5

—

0.5

—

0.5

—

0.5

—

0.5

—

—

ns