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IDT72V3670L15PF Datasheet(PDF) 4 Page - Integrated Device Technology

Part # IDT72V3670L15PF
Description  3.3 VOLT HIGH-DENSITY SUPERSYNC??II 36-BIT FIFO
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V3670L15PF Datasheet(HTML) 4 Page - Integrated Device Technology

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COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
BM
IW
OW
Write Port Width
Read Port Width
L
L
L
x36
x36
H
L
L
x36
x18
H
L
H
x36
x9
H
H
L
x18
x36
H
H
H
x9
x36
TABLE 1  BUS-MATCHING CONFIGURATION MODES
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RTinputduringarisingRCLKedgeinitiatesaretransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero latency retransmit operation is selected, the first data word to be
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK
edge that initiated the retransmit based on RT being LOW.
Refer to Figure 11 and 12 forRetransmit Timingwith normal latency. Refer
to Figure 13 and 14 for Zero Latency Retransmit Timing.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
is configured during master reset by the state of the Big-Endian (
BE)pin.See
Figure 4 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata
written to and read from the FIFO.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the power down state.
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110arefabricatedusingIDT’shighspeedsubmicronCMOS
technology.
NOTE:
1. Pin status during Master Reset.


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