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IDT71421LA35PFI Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT71421LA35PFI Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 16 page 8 IDT7132SA/LA and IDT 7142SA/LA High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 2, Either Side(1) NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. 4. Timing depends on which signal is asserted last, OE or CE. 5. Timing depends on which signal is de-asserted first, OE or CE. Timing Waveform of Read Cycle No. 1, Either Side(1) ADDRESS DATAOUT tRC tOH PREVIOUS DATA VALID tAA tOH DATA VALID 2692 drw 07 tBDDH (2,3) BUSYOUT CE tHZ (5) tLZ (4) tPD (3) VALID DATA tPU 50% OE DATAOUT CURRENT ICC ISS 50% 2692 drw 08 tLZ (4) tHZ (5) tACE tAOE (3) |
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