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IDT74FCT16841BT Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT74FCT16841BT Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 9 page  5.18 8 IDT54/74FCT16841AT/BT/CT/ET, 162841AT/BT/CT/ET FAST CMOS 20-BIT TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES PROPAGATION DELAY SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH SWITCH POSITION Pulse Generator R T D.U.T. V CC VIN C L VOUT 50pF 500 Ω 500 Ω 7.0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU tH tREM tSU tH HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 3V 1.5V 0V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 3V 1.5V 0V tPLH tPHL tPHL VOL CONTROL INPUT 3V 1.5V 0V 3.5V 0V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL 0.3V 0.3V tPLZ tPZL tPZH tPHZ 3.5V 0V 1.5V 1.5V ENABLE DISABLE VOH PRESET CLEAR CLOCK ENABLE ETC. Test Switch Disable Low Enable Low Closed All Other Tests Open Open Drain DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 2556 lnk 11 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 2556 drw 09 2556 drw 07 2556 drw 05 2556 drw 06 2556 drw 08 |
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