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IDT7216L75CB Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT7216L75CB
Description  16 x 16 PARALLEL CMOS MULTIPLIERS
Download  13 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7216L75CB Datasheet(HTML) 7 Page - Integrated Device Technology

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11.3
7
IDT7216L, IDT7217L
16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V
± 10%, TA = 0° to +70°C)
NOTES:
2580 tbl 06
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured
±500mV from steady state voltage.
3. Guaranteed by design, not production tested.
4. Minimum propagation delay times are guaranteed, not production tested.
5. This speed is available in PGA and PLCC packages only.
7216L16(5)
7217L16
7216L20
7217L20
7216L25
7217L25
7216L35
7217L35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tMUC
Unclocked Multiply Time(4)
2
25
2
30
2
38
2
55
ns
tMC
Clocked Multiply Time(4)
2
16
2
20
2
25
2
35
ns
tS
X, Y, RND Set-up Time
10
11
12
12
ns
tH
X, Y, RND Hold Time
1
1
2
3
ns
tPWH
Clock Pulse Width High
7
9
10
10
ns
tPWL
Clock Pulse Width Low
7
9
10
10
ns
tPDSEL
MSPSEL to Product Out(4)
2
15
2
18
2
20
2
25
ns
tPDP
Output Clock to P(4)
2
15
2
18
2
20
2
25
ns
tPDY
Output Clock to Y(4)
2
15
2
18
2
20
2
25
ns
tENA
3-State Enable Time
15
18
20
25
ns
tDIS
3-State Disable Time(2)
15
18
20
22
ns
tS
Clock Enable Set-up Time (IDT7217 only)
9
10
10
10
ns
tH
Clock Enable Hold Time (IDT7217 only)
0
0
2
3
ns
tHCL
Clock Low Hold Time CLKXY
Relative to CLKML (IDT7216 only)(1,3)
0—
0
0—
0
ns
7216L45
7217L45
7216L55
7217L55
7216L65
7217L65
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tMUC
Unclocked Multiply Time(4)
265
2
75
285
ns
tMC
Clocked Multiply Time(4)
245
2
55
265
ns
tS
X, Y, RND Set-up Time
15
20
20
ns
tH
X, Y, RND Hold Time
3
3
3
ns
tPWH
Clock Pulse Width High
15
15
15
ns
tPWL
Clock Pulse Width Low
15
20
20
ns
tPDSEL
MSPSEL to Product Out(4)
225
2
25
230
ns
tPDP
Output Clock to P(4)
225
2
30
230
ns
tPDY
Output Clock to Y(4)
225
2
30
230
ns
tENA
3-State Enable Time
25
30
35
ns
tDIS
3-State Disable Time(2)
—22
25
—25
ns
tS
Clock Enable Set-up Time (IDT7217 only)
10
10
10
ns
tH
Clock Enable Hold Time (IDT7217 only)
3
3
3
ns
tHCL
Clock Low Hold Time CLKXY Relative to CLKML
(IDT7216 only)(1,3)
0—
0—
0—
ns


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