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IDT7200LA25TD Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT7200LA25TD Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 13 page  5 IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS(1) (Continued) (Commercial: VCC = 5V ±10%, TA = 0°C to +70°C; Industrial: VCC = 5V ±10%, TA = –40°C to +85°C; Military: VCC = 5V ±10%, TA = –55°C to +125°C) Military Com'l & Mil. Military (2) 7200 L40 7200L50 7200L65 7200L80 7200L120 7201LA40 7201LA50 7201LA65 7201LA80 7201LA120 7202LA40 7202LA50 7202LA65 7202LA80 7202LA120 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tS Shift Frequency — 20 — 15 — 12.5 — 10 — 7 MHz tRC Read Cycle Time 50 — 65 — 80 — 100 — 140 — ns tA Access Time — 40 — 50 — 65 — 80 — 120 ns tRR Read Recovery Time 10 — 15 — 15 — 20 — 20 — ns tRPW Read Pulse Width (3) 40 — 50 — 65 — 80 — 120 — ns tRLZ Read Pulse Low to Data Bus at Low Z (4) 5 — 10 — 10 — 10 — 10 — ns tWLZ Write Pulse High to Data Bus at Low Z (4, 5) 10 — 15 — 15 — 20 — 20 — ns tDV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — 5 — ns tRHZ Read Pulse High to Data Bus at High Z (4) — 25 — 30 — 30 — 30 — 35 ns tWC Write Cycle Time 50 — 65 — 80 — 100 — 140 — ns tWPW Write Pulse Width (3) 40 — 50 — 65 — 80 — 120 — ns tWR Write Recovery Time 10 — 15 — 15 — 20 — 20 — ns tDS Data Set-up Time 20 — 30 — 30 — 40 — 40 — ns tDH Data Hold Time 0 — 5 — 10 — 10 — 10 — ns tRSC Reset Cycle Time 50 — 65 — 80 — 100 — 140 — ns tRS Reset Pulse Width (3) 40 — 50 — 65 — 80 — 120 — ns tRSS Reset Set-up Time (4) 40 — 50 — 65 — 80 — 120 — ns tRSR Reset Recovery Time 10 — 15 — 15 — 20 — 20 — ns tRTC Retransmit Cycle Time 50 — 65 — 80 — 100 — 140 — ns tRT Retransmit Pulse Width (3) 40 — 50 — 65 — 80 — 120 — ns tRTS Retransmit Set-up Time (4) 40 — 50 — 65 — 80 — 120 — ns tRTR Retransmit Recovery Time 10 — 15 — 15 — 20 — 20 — ns tEFL Reset to Empty Flag Low — 50 — 65 — 80 — 100 — 140 ns tHFH,FFH Reset to Half-Full and Full Flag High — 50 — 65 — 80 — 100 — 140 ns tRTF Retransmit Low to Flags Valid — 50 — 65 — 80 — 100 — 140 ns tREF Read Low to Empty Flag Low — 30 — 45 — 60 — 60 — 60 ns tRFF Read High to Full Flag High — 35 — 45 — 60 — 60 — 60 ns tRPE Read Pulse Width after EF High 40 — 50 — 65 — 80 — 120 — ns tWEF Write High to Empty Flag High — 35 — 45 — 60 — 60 — 60 ns tWFF Write Low to Full Flag Low — 35 — 45 — 60 — 60 — 60 ns tWHF Write Low to Half-Full Flag Low — 50 — 65 — 80 — 100 — 140 ns tRHF Read High to Half-Full Flag High — 50 — 65 — 80 — 100 — 140 ns tWPF Write Pulse Width after FF High 40 — 50 — 65 — 80 — 120 — ns tXOL Read/Write to XO Low — 40 — 50 — 65 — 80 — 120 ns tXOH Read/Write to XO High — 40 — 50 — 65 — 80 — 120 ns tXI XI Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns tXIR XI Recovery Time 10 — 10 — 10 — 10 — 10 — ns tXIS XI Set-up Time 10 — 15 — 15 — 15 — 15 — ns NOTES: 2679 tbl 07 1. Timings referenced as in AC Test Conditions 4. Values guaranteed by design, not currently tested. 2. Speed grades 65, 80 and 120 not available in the CERPACK 5. Only applies to read data flow-through mode. 3. Pulse widths less than minimum value are not allowed. |
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