6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

11

NOTES:

1.

R/

W or CE must be HIGH during all address transitions.

3.

CE or R/W going HIGH to the end of the write cycle.

4.

During this period, the I/O pins are in the output state, and input signals must not be applied.

5.

If the

CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6.

Timing depends on which enable signal (

CE or R/W) is asserted last.

7.

Timing depends on which enable signal is de-asserted first,

CE or OE.

8. If

OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

9. R/

W for either upper or lower byte.

CE

2746 drw 09

ADDRESS

R/

W

(7)

(4)

(2)

OE

(9)

(7)

(6)

(3)

(4)

(7)

CE

2746 drw 10

ADDRESS

R/

W

(9)

(6)

(2)