 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT72240L12TPB Datasheet(PDF) 6 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT72240L12TPB Datasheet(HTML) 6 Page - Integrated Device Technology |
|
|
6 / 16 page  5.12 6 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO ™ 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES When Read Enable ( REN) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from the FIFO, the Empty Flag ( EF) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, the Empty Flag ( EF) will go HIGH after tREF and a valid read can begin. Read Enable ( REN) is ignored when the FIFO is empty. Output Enable ( OE OE) — When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When Output Enable ( OE) is disabled (HIGH), the Q output data bus is in a high-impedance state. OUTPUTS: Full Flag ( FF FF) — The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full. If no reads are performed after Reset ( RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256 writes for the IDT72200, 512 writes for the IDT72210, 1024 writes for the IDT72220, 2048 writes for the IDT72230, and 4096 writes for the IDT72240. The Full Flag ( FF) is synchronized with respect to the LOW- to-HIGH transition of the write clock (WCLK). Empty Flag ( EF EF) — The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The Empty Flag ( EF) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Almost Full Flag ( AF AF) — The Almost Full Flag (AF) will go LOW when the FIFO reaches the Almost-Full condition. If no reads are performed after Reset ( RS), the Almost Full Flag ( AF) will go LOW after 57 writes for the IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1017 writes for the IDT72220, 2041 writes for the IDT72230 and 4089 writes for the IDT72240. The Almost Full Flag ( AF) is synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). Almost Empty Flag ( AE AE) — The Almost Empty Flag (AE) will go LOW when the FIFO reaches the Almost-Empty condition. If no reads are performed after Reset ( RS), the Almost Empty Flag ( AE) will go HIGH after 8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and IDT72240. The Almost Empty Flag ( AE) is synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). Data Outputs (Q0–Q7) — Data outputs for a 8-bit wide data. SIGNAL DESCRIPTIONS INPUTS: Data In (D0–D7) — Data inputs for 8-bit wide data. CONTROLS: Reset ( RS RS) — Reset is accomplished whenever the Reset ( RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. The Full Flag ( FF) and Almost Full Flag (AF) will be reset to HIGH after tRSF. The Empty Flag ( EF) and Almost Empty Flag ( AE) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros. Write Clock (WCLK) — A write cycle is initiated on the LOW- to-HIGH transition of the write clock (WCLK). Data set-up and hold times must be met in respect to the LOW-to-HIGH transition of the write clock (WCLK). The Full Flag ( FF) and Almost Full Flag ( AF) are synchronized with respect to the LOW-to-HIGH transition of the write clock (WCLK). The write and read clocks can be asynchronous or coinci- dent. Write Enable ( WEN WEN) — When Write Enable (WEN) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored in the RAM array sequentially and indepen- dently of any on-going read operation. When Write Enable ( WEN) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag ( FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the Full Flag ( FF) will go HIGH after tWFF, allowing a valid write to begin. Write Enable ( WEN) is ignored when the FIFO is full. Read Clock (RCLK) — Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLK). The Empty Flag ( EF) and Almost-Empty Flag (AE) are synchronized with respect to the LOW-to-HIGH transition of the read clock (RCLK). The write and read clocks can be asynchronous or coinci- dent. Read Enable ( REN REN) — When Read Enable (REN) is LOW, data is read from the RAM array to the output register on the LOW-to-HIGH transition of the read clock (RCLK). |
Similar Part No. - IDT72240L12TPB |
|
Similar Description - IDT72240L12TPB |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
