IDT54/74FCT388915T 70/100/133/150

3.3V LOW SKEW PLL-BASED CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.8

7

Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T

NOTES:

1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure

stable and jitter-free operation:

a.

All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of

long traces can cause undesirable voltage transients at the LF pin.

b.

The 10

µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the

protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system.

c.

The loop filter capacitor (0.1

µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.

2. In addition to the bypass capacitors used in the analog filter of figure 2 there should be a 0.1

µF bypass capacitor between each of the other (digital) four

in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 388915T package as possible.

0.1

µF (Loop

Filter Cap)

Analog loop filter

section of the

FCT388915T

0.1

µF

High

Freq.

Bypass

10

µF

Low

Freq.

Bypass

BOARD GND

ANALOG GND

LF

A separate Analog power supply

is not necessary and should not

be used. Following these

prescribed guidelines is all that is

necessary to use the FCT388915

in a normal digital environment.

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