IDT54/74FCT388915T 70/100/133/150

3.3V LOW SKEW PLL-BASED CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.8

5

Symbol

Parameter

Min.*

Max.*

Unit

All Outputs

Rise/Fall Time

(between 0.8V and 2.0V)

Load = 50

Ω to

1.5

ns

Q,

Output Pulse Width

Q0-Q4,

Q5, Q/2, @ 1.5V

Load = 50

Ω to

ns

Output Pulse Width

2Q @ 1.5V

ns

SYNC input to FEEDBACK delay

(measured at SYNC0 or 1 and FEEDBACK

input pins)

Load = 50

Ω to

0.1

µF from LF to

–0.5

+0.5

ns

Output to Output Skew

between outputs 2Q, Q0-Q4,

Q/2 (rising edges only)

Load = 50

Ω to

—

250

ps

Output to Output Skew

between outputs Q0-Q4 (falling edges only)

—

250

ps

Output to Output Skew

2Q, Q/2, Q0-Q4 rising,

Q5 falling

—

350

ps

Time required to acquire

Phase-Lock from time

SYNC input signal is received

10

ms

Output Enable Time

OE/

RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q

14

ns

Output Disable Time

OE/

RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q

14

ns

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

GENERAL AC SPECIFICATION NOTES:

*

PRELIMINARY.

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested.

3. These specifications are guaranteed but not production tested.

4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.

Q, Q/2 or 2Q) is expected to run.

C1 is loop filter capacitor shown in Figure 2).

3052 tbl 08