IDT74FCT16652ETPA datasheet(7/9 Pages) IDT

Part #	IDT74FCT16652ETPA

Description	FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS

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Manufacturer	IDT [Integrated Device Technology]

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IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET

FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT16652T/162652T

FCT16652AT/162652AT

Com'l.

Mil.

Com'l.

Mil.

Symbol

Parameter

Condition(1)

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Unit

tPLH

tPHL

Propagation Delay

Bus to Bus

CL = 50pF

RL = 500

Ω

2.0

9.0

2.0

11.0

2.0

6.3

2.0

7.7

ns

tPZH

tPZL

Output Enable Time

xOEAB or x

OEBA to Bus

2.0

14.0

2.0

15.0

2.0

9.8

2.0

10.5

ns

tPHZ

tPLZ

Output Disable Time

xOEAB or x

OEBA to Bus

2.0

9.0

2.0

11.0

2.0

6.3

2.0

7.7

ns

tPLH

tPHL

Propagation Delay

Clock to Bus

2.0

9.0

2.0

10.0

2.0

6.3

2.0

7.0

ns

tPLH

tPHL

Propagation Delay xSBA or

xSAB to Bus

2.0

11.0

2.0

12.0

2.0

7.7

2.0

8.4

ns

tSU

Set-up Time HIGH or LOW

Bus to Clock

4.0

—

4.5

—

2.0

—

2.0

—

ns

tH

Hold Time HIGH or LOW

Bus to Clock

2.0

—

2.0

—

1.5

—

1.5

—

ns

tW

Clock Pulse Width

HIGH or LOW

6.0

—

6.0

—

5.0

—

5.0

—

ns

tSK(o) Output Skew(3)

—

0.5

—

0.5

—

0.5

—

0.5

ns

FCT16652CT/162652CT

FCT16652ET/162652ET

Com'l.

Mil.

Com'l.

Mil.

Symbol

Parameter

Condition(1)

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Unit

tPLH

tPHL

Propagation Delay

Bus to Bus

CL = 50pF

RL = 500

Ω

1.5

5.4

1.5

6.0

1.5

3.8

—

ns

tPZH

tPZL

Output Enable Time

xOEAB or x

OEBA to Bus

1.5

7.8

1.5

8.9

1.5

4.8

—

ns

tPHZ

tPLZ

Output Disable Time

xOEAB or x

OEBA to Bus

1.5

6.3

1.5

7.7

1.5

4.0

—

ns

tPLH

tPHL

Propagation Delay

Clock to Bus

1.5

5.7

1.5

6.3

1.5

3.8

—

ns

tPLH

tPHL

Propagation Delay xSBA or

xSAB to Bus

1.5

6.2

1.5

7.0

1.5

4.2

—

ns

tSU

Set-up Time HIGH or LOW

Bus to Clock

2.0

—

2.0

—

2.0

—

ns

tH

Hold Time HIGH or LOW

Bus to Clock

1.5

—

1.5

—

0.0

—

ns

tW

Clock Pulse Width

HIGH or LOW

5.0

—

5.0

—

3.0(4)

———

ns

tSK(o) Output Skew(3)

—

0.5

—

0.5

—

0.5

—

ns

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This limit is guaranteed but not tested.

2549 tbl 09

2549 tbl 10

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