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IDT71256S120DB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT71256S120DB Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 9 page 7.2 6 IDT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 71256S55 (1) 71256S70 (1) 71256S85 (1) 71256S100 (1,3) 71256L55 (1) 71256L70 (1) 71256L85 (1) 71256L100 (1,3) Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55 — 70 — 85 — 100 — ns tAA Address Access Time — 55 — 70 — 85 — 100 ns tACS Chip Select Access Time — 55 — 70 — 85 — 100 ns tCLZ (2) Chip Deselect to Output in Low-Z 5 — 5 — 5 — 5 — ns tCHZ (2) Output Enable to Output in Low-Z — 25 — 30 — 35 — 40 ns tOE Output Enable to Output Valid — 25 — 30 — 35 — 40 ns tOLZ (2) Output Enable to Output in Low-Z 0 — 0 — 0 — 0 — ns tOHZ (2) Output Disable to Output in High-Z 0 25 0 30 — 35 — 40 ns tOH Output Hold from Address Change 5 — 5 — 5 — 5 — ns Write Cycle tWC Write Cycle Time 55 — 70 — 85 — 100 — ns tCW Chip Select to End-of-Write 50 — 60 — 70 — 80 — ns tAW Address Valid to End-of-Write 50 — 60 — 70 — 80 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 40 — 45 — 50 — 55 — ns tWR Write Recovery Time 0 — 0 — 0 — 0 — ns tDW Data to Write Time Overlap 25 — 30 — 35 — 40 — ns tDH Data Hold from Write Time ( WE)0 — 0 — 0 — 0 — ns tWHZ (2) Write Enable to Output in High-Z — 25 — 30 — 35 — 40 ns tOW (2) Output Active from End-of-Write 5 — 5 — 5 — 5 — ns NOTES: 2946 tbl 11 1. –55 °C to +125°C temperature range only. 2. This parameter guaranteed by device characterization, but is not production tested. 3. Also available: 120 and 150 ns military devices. |
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