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IDT74FCT88915TT100PY Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT74FCT88915TT100PY Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 11 page  IDT54/74FCT88915TT 55/70/100/133 LOW SKEW PLL-BASED CMOS CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 9.7 8 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2 frequency. 1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run at 2X the Q frequency. The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the 2Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency. Figure 2c. Wiring Diagram and Frequency Relationships With 2Q Output Feedback Q/2 Q3 Q2 PLL_EN Q1 Q0 FQ_SEL FEEDBACK REF_SEL SYNC(0) VCC(AN) LF GND(AN) Q4 RST Q5 2Q FCT88915TT LOW 50MHz signal 12.5MHz feedback signal HIGH HIGH HIGH 25MHz "Q" Clock Outputs 12.5 MHz input 3072 drw 07 Allowable Input Frequency Range: 10MHz to (f2Q FMAX Spec /4 (for FREQ_SEL HIGH) 5MHz to (f2Q FMAX Spec /8 (for FREQ_SEL LOW) Figure 2a. Wiring Diagram and Frequency Relationships With Q/2 Output Feedback Q/2 Q3 Q2 PLL_EN Q1 Q0 FQ_SEL FEEDBACK REF_SEL SYNC(0) VCC(AN) LF GND(AN) Q4 RST Q5 2Q FCT88915TT LOW 50MHz signal 25MHz feedback signal HIGH HIGH HIGH 25MHz "Q" Clock Outputs 25MHz input 12.5MHz signal 3072 drw 08 Allowable Input Frequency Range: 20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL HIGH) 10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL LOW) Figure 2b. Wiring Diagram and Frequency Relationships With Q4 Output Feedback Q/2 Q3 Q2 PLL_EN Q1 Q0 FQ_SEL FEEDBACK REF_SEL SYNC(0) VCC(AN) LF GND(AN) Q4 RST Q5 2Q FCT88915TT LOW 50MHz feedback signal HIGH HIGH HIGH 25MHz "Q" Clock Outputs 50MHz input 12.5MHz input 3072 drw 09 Allowable Input Frequency Range: 40MHz to (f2Q FMAX Spec) (for FREQ_SEL HIGH) 20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL LOW) |
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