IDT79R3041-20 datasheet(7/34 Pages) IDT

Part #	IDT79R3041-20

Description	INTEGRATED RISController??FOR LOW-COST SYSTEMS

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Manufacturer	IDT [Integrated Device Technology]

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IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS

COMMERCIAL TEMPERATURE RANGE

poke, etc.).

• IDT/kit™ (Kernel Integration Toolkit), providing library sup-

port and a frame work for the system run time environment.

PERFORMANCE OVERVIEW

The RISController family achieves a very high-level of

performance. This performance is based on:

• An efficient execution engine: The CPU performs ALU

operations and store operations in a single cycle, and has

an effective load time of 1.3 cycles, and branch execution

rate of 1.5 cycles (based on the ability of the compilers to

avoid software interlocks). Thus, the R3041 achieves 20

MIPS performance at 25MHz when operating out of cache.

• Large on-chip caches: The RISController family contains

caches which are substantially larger than those on the

majority of embedded microprocessors. These large caches

minimize the number of bus transactions required, and

allow the RISController family to achieve actual sustained

performance very close to its peak execution rate, even with

low-cost memory systems.

• Autonomous multiply and divide operations:

The

RISController family features an on-chip integer multiplier/

divide unit which is separate from the other ALU. This allows

the R3041 to perform multiply or divide operations in parallel

with other integer operations, using a single multiply or

divide instruction rather than using “step” operations.

• Integrated write buffer: The R3041 features a four deep

write buffer, which captures store target addresses and data

at the processor execution rate and retires it to main

memory at the slower main memory access rate. Use of on-

chip write buffers eliminates the need for the processor to

stall when performing store operations.

• Burst read support:

The R3041 enables the system

designer to utilize page mode, static column, or nibble mode

RAMs when performing read operations to minimize the

main memory read penalty and increase the effective cache

hit rates.

The performance differences among the various

RISController family members depends on the application

software and the design of the memory system. Different

family members feature different cache sizes, and the R3081

features a hardware floating point accelerator. Since all these

devices can be used in a pin and software compatible fashion,

the system designer has maximum freedom in trading be-

tween performance and cost. The memory simulation tools

(e.g. Cache3041) allows the system designers to analyze and

understand the performance differences among these de-

vices in their application.

SELECTABLE FEATURES

The RISController family uses two methods to allow the

system designer to configure bus interface operation options.

The first set of options are established via the Reset

Configuration Mode inputs, sampled during the device reset.

After reset, the Reset Mode inputs become regular input or

output signals.

The second set of configuration options are contained in

the System Control Co-Processor registers. These Co-pro-

cessor registers configuration options are typically initialized

with the boot PROM and can also be changed dynamically by

the kernel software.

Selectable features include:

• Big Endian vs. Little Endian operation: The part can be

configured to operate with either byte ordering convention,

and in fact may also be dynamically switched between the

two conventions. This facilitates the porting of applications

from other processor architectures, and also permits inter-

communication between various types of processors and

databases.

• Data Cache Refill of one or four words: The memory

system must be capable of performing 4 word transfers to

satisfy instruction cache misses and 1 word transfers to

satisfy uncached references. The data cache refill size

option allows the system designers to choose between one

and four word refill on data cache misses, depending on the

performance each option brings to their application.

• Bus Turn Around speed: The R3041 allows the kernel to

increase the amount of time between bus transactions

when changes in direction of the A/D bus occur (e.g., at the

end of reads followed by writes). This allows transceivers

and buffers to be eliminated from the system.

• Extended Address Hold Time: The R3041 allows the

system designer to increase the amount of hold time avail-

able for address latching, thus allowing slower speed (low

cost) address latches, FPGAs and ASICs to be used.

• Programmable control signals: The R3041 allows the

system designer to optimally configure various memory

control signals to be active on reads only, writes only, or on

both reads and writes. This allows the simplification of

external logic, thus reducing system cost.

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